74AVC8T245BQ,118 NXP Semiconductors, 74AVC8T245BQ,118 Datasheet

TXRX 8BIT TRANSLATNG DHVQFN24

74AVC8T245BQ,118

Manufacturer Part Number
74AVC8T245BQ,118
Description
TXRX 8BIT TRANSLATNG DHVQFN24
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AVC8T245BQ,118

Logic Family
74AVC
Number Of Channels Per Chip
2
Propagation Delay Time
6 ns, 11.8 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Package / Case
DHVQFN-24
Maximum Power Dissipation
600 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5252-2
1. General description
2. Features
The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (V
and V
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V
referenced to V
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
GND level, both An and Bn are in the high-impedance OFF-state.
I
I
I
I
74AVC8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 02 — 28 April 2009
Wide supply voltage range:
Complies with JEDEC standards:
ESD protection:
Maximum data rates:
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
CC(B)
V
V
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 2.5 V translation)
210 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
CC(A)
CC(B)
can be supplied at any voltage between 0.8 V and 3.6 V making the device
: 0.8 V to 3.6 V
: 0.8 V to 3.6 V
CC(B)
. A HIGH on DIR allows transmission from An to Bn and a LOW on
CC(A)
CC(A)
and V
and pins Bn are
CC(A)
Product data sheet
CC(B)
OFF
or V
). Both V
. The I
CC(B)
are at
OFF
CC(A)

Related parts for 74AVC8T245BQ,118

74AVC8T245BQ,118 Summary of contents

Page 1

Rev. 02 — 28 April 2009 1. General description The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (An ...

Page 2

... NXP Semiconductors I Suspend mode I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages OFF I Multiple package options I Specified from +85 C and +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AVC8T245PW +125 C 74AVC8T245BQ +125 C 4 ...

Page 3

... NXP Semiconductors Fig 2. Logic diagram (one channel) 5. Pinning information 5.1 Pinning 74AVC8T245 V 1 CC(A) 2 DIR GND 11 GND 12 Fig 3. Pin configuration TSSOP24 74AVC8T245_2 Product data sheet 8-bit dual supply translating transceiver; 3-state DIR A1 V CC(A) to other seven channels 24 V CC( CC( GND ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin V 1 CC(A) DIR [1] GND 11 [1] GND 12 [1] GND 21, 20, 19, 18, 17, 16, 15, 14 data input or output CC( CC(B) [1] All GND pins must be connected to ground (0 V). 6. Functional description [1] Table 3. Function table Supply voltage Input ...

Page 5

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I ground current GND T storage temperature stg P total power dissipation tot [1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

Page 6

... NXP Semiconductors Table 6. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF C input capacitance I C input/output capacitance I/O [ the supply voltage associated with the output port. CCO [ the supply voltage associated with the data input port. ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage I = 100 CC( mA CC( mA CC( mA CC( mA CC( mA CC(A) V LOW-level output voltage I = 100 CC( mA CC( mA CC( mA CC( mA CC( mA CC(A) I input leakage DIR, OE input; V ...

Page 8

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current A port CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(A) B port CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(A) A plus B port ( CC(A) V CC(B) A plus B port ( CC(A) V CC(B) ...

Page 9

... NXP Semiconductors 10. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay disable time dis enable time [ the same as t and PLH PHL Table 10. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see ...

Page 10

... NXP Semiconductors Table 11. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction capacitance Bn); output enabled A port: (direction An to Bn); output disabled A port: (direction Bn to An); output enabled A port: (direction Bn to An); output disabled B port: (direction An to Bn) ...

Page 11

... NXP Semiconductors Table 12. Dynamic characteristics for temperature range +85 C Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation delay disable time dis enable time 1 1.6 V CC(A) t propagation delay disable time dis enable time ...

Page 12

... NXP Semiconductors Table 13. Dynamic characteristics for temperature range +125 C Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation delay disable time dis enable time 1 1.6 V CC(A) t propagation delay disable time dis enable time ...

Page 13

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...

Page 14

... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance External voltage for measuring switching times. EXT Fig 7. Load circuit for switching times Table 15. Test data Supply voltage Input [ CC(A) CC( CCI 1. 2.7 V ...

Page 15

... NXP Semiconductors 12. Typical propagation delay characteristics (ns Propagation delay (An to Bn 0.8 V. CC(B) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 8. Typical propagation delay versus load capacitance; T 74AVC8T245_2 Product data sheet 8-bit dual supply translating transceiver; 3-state 001aai476 (1) (ns) ...

Page 16

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.2 V CC( PLH (ns LOW to HIGH propagation delay ( 1.5 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 9. Typical propagation delay versus load capacitance; T 74AVC8T245_2 Product data sheet 8-bit dual supply translating transceiver; 3-state ...

Page 17

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.8 V CC( PLH (ns LOW to HIGH propagation delay ( 2.5 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 10. Typical propagation delay versus load capacitance; T 74AVC8T245_2 Product data sheet 8-bit dual supply translating transceiver; 3-state ...

Page 18

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 3.3 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 11. Typical propagation delay versus load capacitance; T 74AVC8T245_2 Product data sheet 8-bit dual supply translating transceiver; 3-state 001aai485 t PHL (1) (ns) ...

Page 19

... NXP Semiconductors 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors 14. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 17. Revision history Document ID Release date 74AVC8T245_2 20090428 • Modifications: Section 5 “ ...

Page 22

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Typical propagation delay characteristics Package outline ...

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