74ALVC164245BQ,518 NXP Semiconductors, 74ALVC164245BQ,518 Datasheet
74ALVC164245BQ,518
Specifications of 74ALVC164245BQ,518
Related parts for 74ALVC164245BQ,518
74ALVC164245BQ,518 Summary of contents
Page 1
Rev. 05 — 13 April 2010 1. General description The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245 is a 16-bit (dual ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Temperature range −40 °C to +125 °C 74ALVC164245DL 74ALVC164245DGG −40 °C to +125 °C −40 °C to +125 °C 74ALVC164245BQ 4. Functional diagram 1DIR 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 Fig 1. Logic symbol 74ALVC164245_5 Product data sheet 16-bit dual supply translating transceiver ...
Page 3
... NXP Semiconductors Fig 2. IEC logic symbol 74ALVC164245_5 Product data sheet 16-bit dual supply translating transceiver; 3-state 1OE G3 1DIR 3EN1[BA] 3EN2[AB] G6 2OE 2DIR 6EN1[BA] 6EN2[AB] 1A0 1B0 1 2 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1A5 1B5 1B6 1A6 1A7 1B7 ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 74ALVC164245_5 Product data sheet 16-bit dual supply translating transceiver; 3-state 1DIR 1 1B0 2 3 1B1 4 GND 1B2 5 1B3 CC(B) 8 1B4 9 1B5 GND 10 1B6 11 1B7 12 74ALVC164245 13 2B0 14 2B1 GND ...
Page 5
... NXP Semiconductors terminal 1 index area (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SOT1134-1 (HXQFN60U) 74ALVC164245_5 Product data sheet 16-bit dual supply translating transceiver; 3-state D1 A32 A31 A30 ...
Page 6
... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 1B0 to 1B7 11, 12 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 CC(B) 1OE, 2OE 48, 25 1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 ...
Page 7
... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See [1] . Symbol Parameter I ground current GND T storage temperature stg P total power dissipation tot [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 ° ...
Page 8
... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level nBn port IH input voltage V CC(B) nAn port, nOE and nDIR V CC(A) V CC(A) V LOW-level nBn port IL input voltage V CC(B) V CC(B) nAn port, nOE and nDIR ...
Page 9
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current ΔI additional per control pin; CC supply current input I capacitance C input/output nAn and nBn port I/O capacitance [1] All typical values are measured < ...
Page 10
... NXP Semiconductors Table 7. Dynamic characteristics ≤ GND = 2.5 ns pF; for test circuit see Symbol Parameter Conditions t enable time nOE to nBn; see en V CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(B) nOE to nAn; see V CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(B) t disable time nOE to nBn; see ...
Page 11
... NXP Semiconductors Table 7. Dynamic characteristics ≤ GND = 2.5 ns pF; for test circuit see Symbol Parameter Conditions C power 5 V port: nAn to nBn; PD dissipation V CC(B) capacitance outputs enabled outputs disabled 3 V port: nBn to nAn; V CC(B) outputs enabled outputs disabled [1] All typical values are measured at nominal voltage for V ...
Page 12
... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with output load Fig 6. 3-state enable and disable times Table 8. Measurement points Direction Supply voltage V CC(A) nAn port to nBn 2 ...
Page 13
... NXP Semiconductors Test data is given in Table Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance. L Fig 7. Load circuitry for switching times Table 9. Test data Direction Supply voltage V CC(A) nAn port to nBn 2 ...
Page 14
... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE ...
Page 15
... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 16
... NXP Semiconductors HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 0.5 mm terminal 1 index area A10 terminal 1 index area D1 Dimensions Unit max 0.50 0.05 0.35 4.1 mm nom 0.48 0.02 0.30 4.0 min 0.46 0.00 0.25 3.9 ...
Page 17
... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74ALVC164245_5 20100413 • Modifications: 74ALVC164245BQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package ...
Page 18
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 19
... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ALVC164245_5 Product data sheet 16-bit dual supply translating transceiver; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 05 — 13 April 2010 74ALVC164245 © ...
Page 20
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Abbreviations ...