JS28F128P30BF75A

Manufacturer Part NumberJS28F128P30BF75A
DescriptionIC FLASH 128MBIT 65NM 56TSOP
ManufacturerNUMONYX
SeriesAxcell™
JS28F128P30BF75A datasheet
 

Specifications of JS28F128P30BF75A

Format - MemoryFLASHMemory TypeFLASH
Memory Size128M (8Mx16)Speed75ns
InterfaceParallelVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case56-TFSOP (0.551", 14.00mm Width)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Numonyx™ StrataFlash
(P30)
Product Features
High performance
— 85 ns initial access
— 52 MHz with zero wait states, 17ns clock-to-data output
synchronous-burst read mode
— 25 ns asynchronous-page read mode
— 4-, 8-, 16-, and continuous-word burst mode
— Buffered Enhanced Factory Programming (BEFP) at 5 μs/
byte (Typ)
— 1.8 V buffered programming at 7 μs/byte (Typ)
Architecture
— Multi-Level Cell Technology: Highest Density at Lowest
Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or bottom
configuration
— 128-KByte main blocks
Voltage and Power
— V
(core) voltage: 1.7 V – 2.0 V
CC
— V
(I/O) voltage: 1.7 V – 3.6 V
CCQ
— Standby current: 20μA (Typ) for 64-Mbit
— 4-Word synchronous read current:
13 mA (Typ) at 40 MHz
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology
®
Embedded Memory
Security
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
• 2112 user-programmable OTP bits
— Selectable OTP Space in Main Array:
• Four pre-defined 128-KByte blocks (top or bottom
configuration)
• Up to Full Array OTP Lockout
— Absolute write protection: V
= V
PP
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
— 20 μs (Typ) program suspend
— 20 μs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Command Set
compatible
— Common Flash Interface capable
Density and Packaging
— 56- Lead TSOP package (64, 128, 256,
512- Mbit)
— 64- Ball Numonyx™ Easy BGA package (64,
128, 256, 512- Mbit)
— Numonyx™ QUAD+ SCSP (64, 128, 256,
512- Mbit)
— 16-bit wide data bus
Datasheet
SS
306666-12
August 2008

JS28F128P30BF75A Summary of contents

  • Page 1

    ... Common Flash Interface capable Density and Packaging — 56- Lead TSOP package (64, 128, 256, 512- Mbit) — 64- Ball Numonyx™ Easy BGA package (64, 128, 256, 512- Mbit) — Numonyx™ QUAD+ SCSP (64, 128, 256, 512- Mbit) — 16-bit wide data bus ...

  • Page 2

    ... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. ...

  • Page 3

    ... P30 Contents 1.0 Functional Description ............................................................................................... 5 1.1 Introduction ....................................................................................................... 5 1.2 Overview ........................................................................................................... 5 1.3 Virtual Chip Enable Description.............................................................................. 6 1.4 Memory Maps ..................................................................................................... 6 2.0 Package Information ................................................................................................. 9 2.1 56-Lead TSOP..................................................................................................... 9 2.2 64-Ball Easy BGA Package .................................................................................. 10 2.3 QUAD+ SCSP Packages ...................................................................................... 12 3.0 Ballouts ................................................................................................................... 15 4.0 Signals .................................................................................................................... 18 4.1 Dual-Die Configurations ..................................................................................... 20 5.0 Bus Operations ........................................................................................................ 21 5 ...

  • Page 4

    Lock-Down Block ....................................................................................36 10.1.4 Block Lock Status ...................................................................................37 10.1.5 Block Locking During Suspend ..................................................................37 10.2 Selectable One-Time Programmable Blocks ...........................................................38 11.0 Registers .................................................................................................................39 11.1 Read Status Register..........................................................................................39 11.1.1 Clear Status Register ..............................................................................40 11.2 Read Configuration Register ................................................................................40 11.2.1 Read ...

  • Page 5

    ... Functional Description 1.1 Introduction This document provides information about the Numonyx™ StrataFlash Memory (P30) product and describes its features, operation, and specifications. The Numonyx™ StrataFlash of Numonyx™ StrataFlash densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment ...

  • Page 6

    The P30 protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the ...

  • Page 7

    ... F60000 - F6FFFF 128 1 010000 - 01FFFF 128 0 000000 - 00FFFF August 2008 Order Number: 306666-12 Table 5 show the P30 memory maps. The memory array is divided into Section 8.0, “Program Operation” on 64-Mbit Size Blk 128-Mbit (KB) 32 130 7FC000 - 7FFFFF 32 127 7F0000 - 7F3FFF ...

  • Page 8

    ... Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K- Words where a Word is the size of the flash output bus (16 bits). Note: The Dual- Die P30 memory maps are the same for both parameter options because the devices employ virtual chip enable (Refer to the placement of bottom parameter die. ...

  • Page 9

    ... P30 Table 5: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP) Die Stack Config 256-Mbit Top Parameter Die 256-Mbit Bottom Parameter Die Note: Refer to the appropriate 256-Mbit Memory Map ( is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of the flash output bus (16 bits) ...

  • Page 10

    Package Information 2.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 6: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A Standoff ...

  • Page 11

    ... If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. 2.2 64-Ball Easy BGA Package ...

  • Page 12

    ... Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Notes: 1. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. Datasheet 12 Millimeters Symbol Min Nom Max ...

  • Page 13

    P30 2.3 QUAD+ SCSP Packages Figure 3: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark Top View - Ball Down ...

  • Page 14

    Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball Down A2 Note: Dimensions A1, A2, ...

  • Page 15

    P30 Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package ...

  • Page 16

    ... Please refer to the latest specification update for synchronous read operation with the TSOP package. The synchronous read input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See Datasheet 16 Intel StrataFlash® Embedded Memory (P30) 56-Lead TSOP Pinout Top View Section 4.0, “Signals” on page 19 ...

  • Page 17

    P30 Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 ...

  • Page 18

    Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin A18 C A5 RFU D A3 A17 DQ8 H RFU DQ0 J RFU F1-OE# K ...

  • Page 19

    ... WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock- WP# Input down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V not be attempted. Set ...

  • Page 20

    ... Table 8: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. RFU — These should be treated in the same way Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. ...

  • Page 21

    ... Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. RFU — These should be treated in the same way Not Use (DU) signal. DU — ...

  • Page 22

    ... Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted ...

  • Page 23

    ... CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU ...

  • Page 24

    ... The confirm command is Issued after the data streaming for writing into the buffer is done. This instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP) ...

  • Page 25

    P30 Table 11: Command Codes and Definitions (Sheet Mode Code Device Mode 0x20 Block Erase Setup Erase 0xD0 Block Erase Confirm Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Lock Block Setup 0x01 Lock Block ...

  • Page 26

    ... DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device) DnA = Address within the device Identification code address offset. CFI-A = Read CFI address offset Word address of memory location to be written Address within the block. OTP-RA = Protection Register address. LRA = Lock Register address. ...

  • Page 27

    ... AVQV In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time ...

  • Page 28

    Read Device Identifier The Read Device Identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data. Table 13: Device Identifier Information Item Manufacturer Code Device ID Code Block ...

  • Page 29

    ... Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see The Status Register can be examined for programming progress and errors by reading at any address ...

  • Page 30

    ... The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. ...

  • Page 31

    ... Flowchart” on page across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’ ...

  • Page 32

    ... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. ...

  • Page 33

    P30 only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[ and the device is ready for the next buffer fill. Note: Any ...

  • Page 34

    Program Protection When absolute hardware write protection is provided for all device blocks below V PP level error. Block lock registers are not affected by the voltage level ...

  • Page 35

    ... Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation read operation within any block except the block that is erase suspended (see Figure 35, “ ...

  • Page 36

    Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. V while in ...

  • Page 37

    ... Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. ...

  • Page 38

    Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 12.0, “Power and Reset Specifications” on page the addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 ...

  • Page 39

    ... When programming the OTP bits for a Top Parameter Device, the following upper address bits must also be driven properly: A[Max:17] driven high (V SCSP. Note: Please see your local Numonyx representative for details about the Selectable OTP implementation. August 2008 Order Number: 306666-12 ...

  • Page 40

    Registers When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...

  • Page 41

    P30 Table 18: Status Register Description (Sheet Status Register (SR) 2 Program Suspend Status (PSS) 1 Block-Locked Status (BLS) 0 BEFP Status (BWS) Note: Always clear the Status Register prior to resuming erase operations. It avoids Status ...

  • Page 42

    Table 19: Read Configuration Register Description (Sheet Latency Count (LC[2:0]) 13:11 Wait Polarity (WP) 10 Data Hold (DH Wait Delay (WD) Burst Sequence (BS) 7 Clock Edge (CE) 6 5:4 Reserved (R) Burst Wrap (BW) ...

  • Page 43

    P30 Figure 13: First-Access Latency Count CLK [C] Address [A] Valid Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Valid 15-0 Output Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 ...

  • Page 44

    Figure 14: Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] D[15:0] 11.2.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V WAIT. When WP is set, WAIT is asserted high (default). When WP ...

  • Page 45

    ... When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for ...

  • Page 46

    Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. lengths, as well as the effect of the Burst Wrap (BW) setting. Table 22: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word ...

  • Page 47

    ... The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the OTP Register(s) to prevent additional bit programming (see “ ...

  • Page 48

    Each OTP Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated OTP Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when ...

  • Page 49

    P30 11.3.2 Programming the OTP Registers To program any of the OTP Registers, first issue the Program OTP Register command at the parameter’s base address plus the offset to the desired OTP Register (see 6.0, “Command Set” on page same ...

  • Page 50

    ... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...

  • Page 51

    ... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground ...

  • Page 52

    Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 24: Maximum Ratings Parameter Temperature under bias Storage temperature Voltage on ...

  • Page 53

    P30 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 26: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], LO WAIT Current 64-Mbit 128-Mbit Standby, CCS CC I ...

  • Page 54

    Table 26: DC Current Characteristics (Sheet Sym Parameter I V Erase Current PPE PP Notes: 1. All currents are RMS unless noted. Typical values at typical the average current measured over any 5 ...

  • Page 55

    P30 15.0 AC Characteristics 15.1 AC Test Conditions Figure 18: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst ...

  • Page 56

    Capacitance Table 29: Capacitance Parameter Signals Address, Data, CE#, WE#, OE#, Input Capacitance RST#, CLK, ADV#, WP# Output Capacitance Data, WAIT Notes: 1. Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values ...

  • Page 57

    P30 Table 30: AC Read Specifications for 64/128- Mbit Densities (Sheet Num Symbol R108 t Page address access APA R111 t RST# high to ADV# high phvh Clock Specifications R200 f CLK frequency CLK R201 t CLK ...

  • Page 58

    Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R3 t CE# low to output valid ELQV R4 t OE# low to output valid GLQV R5 t RST# high to output valid PHQV R6 t ...

  • Page 59

    P30 Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 t ...

  • Page 60

    Figure 21: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 22: Asynchronous Single-Word Read ...

  • Page 61

    ... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. August 2008 ...

  • Page 62

    Figure 25: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Notes: 1. WAIT ...

  • Page 63

    P30 15.4 AC Write Specifications Table 33: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data ...

  • Page 64

    Figure 27: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 28: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] ...

  • Page 65

    P30 Figure 29: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [ WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 30: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address ...

  • Page 66

    Figure 31: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, ...

  • Page 67

    P30 16.0 Program and Erase Characteristics Table 34: Program and Erase Specifications Num Symbol Parameter Single word - 130nm Program W200 t Single word - 65nm PROG/W Time Single cell W200 t Single word Program PROG/W Time W251 t 32-word ...

  • Page 68

    ... TE28F128P30B85 TE28F128P30T85 JS28F128P30B85 JS28F128P30T85 RC28F128P30B85 RC28F128P30T85 PC28F128P30B85 PC28F128P30T85 Access Speed 85 ns Parameter Location B = Bottom Parameter T = Top Parameter Product Fam ily P30 = Intel StrataFlash® Embedded Memory V = 1.7 – 2 1.7 – 3.6 V CCQ 256-Mbit TE28F256P30B95 TE28F256P30T95 JS28F256P30B95 JS28F256P30T95 RC28F256P30B85 RC28F256P30T85 PC28F256P30B85 ...

  • Page 69

    ... Intel SCSP, lead-free RC = 64-Ball Easy BG A, leaded 64-Ball Easy BG A, lead-free 56-Lead TSO P , leaded JS = 56-Lead lead-free Group Designator 48F = Flash Memory only Flash Density die 2 = 64-Mbit 3 = 128-M bit 4 = 256-M bit Product Fam ily P = Intel StrataF lash® Em bedded M em ory ...

  • Page 70

    Appendix A Supplemental Reference Information A.1 Common Flash Interface Tables The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read ...

  • Page 71

    ... BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord). 3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended CFI Table. A.1.3 Read CFI Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...

  • Page 72

    Table 41: System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 1 20h 1 21h 1 22h 1 23h 1 24h 1 25h 1 26h 1 Datasheet 72 Description V logic supply minimum program/erase voltage ...

  • Page 73

    P30 A.1.4 Device Geometry Definition Table 42: Device Geometry Definition Offset Length 1 27h 28h 2 2Ah 2 2Ch 1 2Dh 4 31h 4 35h 4 A ddress 27: 28: 29 2B: 2C: 2D: 2E: 2F: 30: 31: ...

  • Page 74

    ... A.1.5 Numonyx-Specific Extended CFI Table Table 43: Primary Vendor-Specific Extended CFI (1) Length Offset P = 10Ah (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 11– ...

  • Page 75

    P30 Table 44: Protection Register Information (1) Length Offset P = 10Ah (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h (P+13)h 10 (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h Table 45: Burst Read Information (1) Length Offset P = ...

  • Page 76

    Table 46: Partition and Erase Block Region Information (1) Offset P = 10Ah Bottom Top Number of device hardware-partition regions within the device single hardware partition device (no fields follow). x specifies the number of device ...

  • Page 77

    P30 Table 48: Partition Region 1 Information (continued) (1) Offset P = 10Ah Bottom Top (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0– y identical-size erase blks in a partition ...

  • Page 78

    Table 49: Partition and Erase Block Region Information Address 64-Mbit –B 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --03 137: --00 138: --80 139: --00 13A: --64 --00 ...

  • Page 79

    ... Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table (P+4A)h Bits 10–27 = nth 32Mbit segment of referenced CFI table (P+4B)h Bits 28–30 = Memory Type Bit 31 = Another CFI Link field immediately follows (P+4C)h 1 CFI Link Field Quantity Subfield definitions Bits 0–3 = Quantity field (n such that n+1 equals quantity) Bit 4 = Table & ...

  • Page 80

    A.2 Flowcharts Figure 34: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register 1 SR[ ...

  • Page 81

    P30 Figure 35: Program Suspend/Resume Flowchart Start Read Status Write 70 h Program Suspend Write B0h Any Address Read Status Register Read Array Write FFh Read Array Data Done No Reading Yes ...

  • Page 82

    Figure 36: Buffer Program Flowchart Start Device Use Single Word Supports Buffer No Programming Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read Status Register (at Block Address) ...

  • Page 83

    P30 Figure 37: BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Start V applied P P Block Unlocked W rite 80h @ ord Address Write D0h @ ord Address BEFP Setup delay ...

  • Page 84

    Figure 38: Block Erase Flowchart BLOCK ERASE PROCEDURE Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register No Suspend 0 Yes SR[7] = Erase 1 Full Erase Status Check (if desired) Block Erase ...

  • Page 85

    P30 Figure 39: Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register 0 SR Erase 0 SR.6 = Completed 1 Read Read or ...

  • Page 86

    Figure 40: Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change? Yes Read Array ...

  • Page 87

    P30 Figure 41: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete FULL ...

  • Page 88

    Figure 42: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Program Ready Ready Setup Lock/CR Setup Ready (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend ...

  • Page 89

    P30 Figure 43: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend ...

  • Page 90

    Figure 44: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) OTP Ready Setup Ready Lock/CR Setup (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend Setup BP Load 1 BP Confirm ...

  • Page 91

    P30 Figure 45: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) Setup Busy Word Program in Erase Suspend Suspend Setup BP Load 1 BP Confirm if Data load into Program Buffer is ...

  • Page 92

    Figure 46: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Setup (3,4) Current chip state (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, ...

  • Page 93

    ... To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation ...

  • Page 94

    The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of ...

  • Page 95

    P30 Appendix B Conventions - Additional Information B.1 Conventions VCC: Signal or voltage connection V : Signal or voltage level CC 0x: Hexadecimal number prefix 0b: Binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of ...

  • Page 96

    ... Migration Guide for Spansion* S29GLxxxN to Numonyx™ StrataFlash 306668 Application Note 813 Note: Contact your local Numonyx or distribution sales office or visit Numonyx’s World Wide Web home page at www.numonyx.com for technical documentation, tools, or the most current information on Numonyx™ Flash Memory. Datasheet ...

  • Page 97

    ... Added EOWL description. • Updated flowcharts • Updated for 65nm lithography • Added W602 - Erase to Suspend • Applied Numonyx branding. • Corrected single word (65 nm) program time from 125 (typ) and 150 (max) to Table 34, “Program and Erase 150 (typ) and 456 (max) in Specifications” ...