JS28F128P30BF75A NUMONYX, JS28F128P30BF75A Datasheet - Page 20

• Manufacturer Part Number: JS28F128P30BF75A
• Description: IC FLASH 128MBIT 65NM 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of JS28F128P30BF75A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TFSOP (0.551", 14.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
Table 9:
Datasheet
20
RFU
DU
NC
A[MAX:0]
DQ[15:0]
ADV#
F1-CE#
CLK
F1-OE#
RST#
WAIT
WE#
WP#
VPP
Symbol
Symbol
TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)
Power/
Output
Output
Input/
Type
Type
Input
Input
Input
Input
Input
Input
Input
Input
lnput
—
—
—
Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.
These should be treated in the same way as a Do Not Use (DU) signal.
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
No Connect: No internal connection; can be driven or floated.
ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit:
A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the
dual-die 512-Mbit configuration is accomplished by setting A[25] high (V
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be driven high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During
synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid
CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V
V
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
not be attempted.
Set V
from the system supply, the V
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
• In asynchronous page mode, and all write modes, WAIT is deasserted.
OH
PPH
when CE# and OE# are V
valid data when deasserted.
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PP
= V
PPL
for in-system program and erase operations. To accommodate resistor or diode drops
IL
IH
. WAIT is high-Z if CE# or OE# is V
level of V
PP
≤ V
Name and Function
Name and Function
PPLK
PP
. Block erase and program at invalid V
can be as low as V
PPL
min. V
IH
.
IH
PP
).
must remain above V
PP
voltages should
August 2008
306666-12
OL
PPL
P30
or