JS28F128P30BF75A NUMONYX, JS28F128P30BF75A Datasheet - Page 35

• Manufacturer Part Number: JS28F128P30BF75A
• Description: IC FLASH 128MBIT 65NM 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of JS28F128P30BF75A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TFSOP (0.551", 14.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P30
9.0
9.1
9.2
August 2008
Order Number: 306666-12
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to
be erased (see
is written to the address of the block to be erased. If the device is placed in standby (CE#
deasserted) during an erase operation, the device completes the erase operation before
entering standby.V
Erase Flowchart” on page
During a block erase, the Write State Machine (WSM) executes a sequence of
internally-timed events that conditions, erases, and verifies all bits within the block.
Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are
ones can be changed to zeros only by programming the block (see
“Program Operation” on page
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR[0] indicates whether the addressed block is erasing. Status
Register bit SR[7] is set upon erase completion.
Status Register bit SR[7] indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR[5] indicates an erase
failure if set. SR[3] set would indicate that the WSM could not perform the erase
operation because V
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 35, “Program Suspend/Resume Flowchart” on page
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
Section 6.0, “Command Set” on page
Section 16.0, “Program and Erase Characteristics” on page
PP
PP
must be above V
was outside of its acceptable limits. SR[1] set indicates that the
84).
29).
PPLK
and the block must be unlocked (see
24). Next, the Block Erase Confirm command
81).
Section 8.0,
Figure 38, “Block
67.
Datasheet
35