JS28F128P30BF75A NUMONYX, JS28F128P30BF75A Datasheet - Page 49

• Manufacturer Part Number: JS28F128P30BF75A
• Description: IC FLASH 128MBIT 65NM 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of JS28F128P30BF75A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TFSOP (0.551", 14.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P30
11.3.2
Note:
11.3.3
Caution:
August 2008
Order Number: 306666-12
Programming the OTP Registers
To program any of the OTP Registers, first issue the Program OTP Register command at
the parameter’s base address plus the offset to the desired OTP Register (see
6.0, “Command Set” on page
same OTP Register address (see
The device programs the 64-bit and 128-bit user-programmable OTP Register data 16
bits at a time (see
page
address space causes a program error (SR[4] set). Attempting to program a locked
OTP Register causes a program error (SR[4] set) and a lock error (SR[1] set).
When programming the OTP bits in the OTP registers for a Top Parameter Device,
the following upper address bits must also be driven properly: A[Max:17] driven high
(V
SCSP.
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see
Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used
when programming the lock registers (see
page
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the
“factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP
Register containing the unique identification number of the device. Bit 1 of Lock
Register 0 can be programmed by the user to lock the user-programmable, 64-bit
region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all
other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of
the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP
Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP
Register.
After being locked, the OTP Registers cannot be unlocked.
IH
) for TSOP and Easy BGA packages, and A[Max:16] driven high (V
87). Issuing the Program OTP Register command outside of the OTP Register’s
28).
Section 6.0, “Command Set” on page
Figure 41, “Protection Register Programming Flowchart” on
24). Next, write the desired OTP Register data to the
Figure 16, “OTP register map” on page
Table 13, “Device Identifier Information” on
24). The physical addresses of the Lock
IH
) for QUAD+
48).
Section
Datasheet
49