IC FLASH 256MBIT 100NS 64EZBGA

RC28F256P30BFA

Manufacturer Part NumberRC28F256P30BFA
DescriptionIC FLASH 256MBIT 100NS 64EZBGA
ManufacturerNUMONYX
SeriesAxcell™
RC28F256P30BFA datasheet
 

Specifications of RC28F256P30BFA

Format - MemoryFLASHMemory TypeFLASH
Memory Size256M (16Mx16)Speed100ns
InterfaceParallelVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case64-EZBGA
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names898885
898885
RC28F256P30BF 898885
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®
Numonyx
Axcell
65nm)
256-Mbit, 512-Mbit (256M/256M)
Product Features
High performance
— 100 ns initial access for Easy BGA
— 110 ns initial access for TSOP
— 25 ns 16-word asynchronous-page read mode
— 52 MHz (Easy BGA) with zero WAIT states,
17ns clock-to-data output synchronous-burst
read mode
— 4-, 8-, 16-, and continuous-word options for
burst mode
— Buffered Enhanced Factory Programming
(BEFP) at 2.0 MByte/s (Typ) using 512-word
buffer
— 1.8 V buffered programming at 1.14 MByte/s
(Typ) using 512-word buffer
Architecture
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Blank Check to verify an erased block
Voltage and Power
— V
(core) voltage: 1.7 V – 2.0 V
CC
— V
(I/O) voltage: 1.7 V – 3.6 V
CCQ
— Standby current: 65 µA (Typ) for 256-Mbit;
— 52 MHz continuos synchronous read current:
21mA (Typ)/24mA(Max)
Datasheet
1
TM
Flash Memory (P30-
Security
— One-Time Programmable Register:
• 64 OTP bits, programmed with unique
information by Numonyx
• 2112 OTP bits, available for customer
programming
— Absolute write protection: V
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Password Access feature
Software
— 25 µs (Typ) program suspend
— 25 µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— Numonyx™ QUAD+ SCSP (256, 512-Mbit)
— 16-bit wide data bus
Quality and Reliability
— JESD47E Compliant
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— 65nm process technology
Datasheet
= V
PP
SS
Mar 2010
Order Number: 320002-10

RC28F256P30BFA Summary of contents

  • Page 1

    ... Common Flash Interface capable Density and Packaging — 56-Lead TSOP package (256-Mbit only) — 64-Ball Easy BGA package (256, 512-Mbit) — Numonyx™ QUAD+ SCSP (256, 512-Mbit) — 16-bit wide data bus Quality and Reliability — JESD47E Compliant — Operating temperature: –40 °C to +85 °C — ...

  • Page 2

    ... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. ...

  • Page 3

    ... P30 - 65 nm Contents 1.0 Functional Description ............................................................................................... 5 1.1 Introduction ....................................................................................................... 5 1.2 Overview ........................................................................................................... 5 1.3 Virtual Chip Enable Description.............................................................................. 6 1.4 Memory Maps ..................................................................................................... 7 2.0 Package Information ................................................................................................. 8 2.1 56-Lead TSOP..................................................................................................... 8 2.2 64-Ball Easy BGA Package .................................................................................. 10 2.3 QUAD+ SCSP Packages ...................................................................................... 11 3.0 Ballouts ................................................................................................................... 13 4.0 Signals .................................................................................................................... 16 4.1 Dual-Die Configurations ..................................................................................... 18 5.0 Bus Operations ...

  • Page 4

    One-Time-Programmable (OTP) Registers .............................................................45 12.0 Power and Reset Specifications ...............................................................................48 12.1 Power-Up and Power-Down .................................................................................48 12.2 Reset Specifications ...........................................................................................48 12.3 Power Supply Decoupling....................................................................................49 13.0 Maximum Ratings and Operating Conditions ............................................................50 13.1 Absolute Maximum Ratings .................................................................................50 13.2 Operating Conditions..........................................................................................50 14.0 ...

  • Page 5

    ... Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The P30-65nm product family is manufactured using Numonyx 65nm process technology. 1.2 Overview This section provides an overview of the features and capabilities of the P30-65nm. ...

  • Page 6

    Virtual Chip Enable Description The P30-65nm 512-Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA packages. Refer to maximum address bit is ...

  • Page 7

    ... P30-65nm 1.4 Memory Maps Figure 1: P30-65nm Memory Map A<24:1 > 256 Mbit (Easy BGA, TSOP) A<23: 0 > 256 Mbit (QUAD+) 64- Kword Block FF 0000 - FFFFFF 64- Kword Block 7F 0000 - 7FFFFF 64- Kword Block 3 F0000 - 3FFFFF 020000 – 02 FFFF 64- Kword Block 010000 – 01 FFFF 64- Kword Block 00C000 – ...

  • Page 8

    Package Information 2.1 56-Lead TSOP Figure 2: TSOP Mechanical Specifications (256-Mbit) Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A ...

  • Page 9

    P30-65nm Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Tip Length L Lead Count N Lead Tip Angle θ Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes ...

  • Page 10

    Easy BGA Package Figure 3: Easy BGA Mechanical Specifications (256-Mbit, 512-Mbit) Ball A1 Corner Top View - Ball side down A1 A2 Table ...

  • Page 11

    P30-65nm 2.3 QUAD+ SCSP Packages Figure 4: 88-ball (80 active) QUAD+ SCSP Specifications (256-Mbit, 8x11x1.0 mm Index Mark Top View - Ball Down ...

  • Page 12

    Figure 5: 88-ball (80 active) QUAD+ SCSP Specifications (512-Mbit, 8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package Height ...

  • Page 13

    ... No Internal Connection on Pin 13; it may be driven or floated. For legacy designs VCC pin and can be tied to Vcc. 4. One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the product mark. Datasheet 13 ® Numonyx TM Axcell Flash Memory (P30) 56-Lead TSOP Pinout Top View ...

  • Page 14

    Figure 7: 64-Ball Easy BGA Ballout (256-Mbit, 512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 ...

  • Page 15

    P30-65nm Figure 8: QUAD+ SCSP Ballout and Signals Pin A18 B A5 RFU A17 DQ8 H RFU DQ0 J RFU OE# K F1-CE# ...

  • Page 16

    ... ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When ...

  • Page 17

    ... P30-65nm Table 5: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and RFU — enhancement. These should be treated in the same way Not Use (DU) signal. DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating. ...

  • Page 18

    ... Power OUTPUT POWER SUPPLY: Output-driver source voltage. VSS Power GROUND: Connect to system ground. Do not float any VSS connection. RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and RFU — enhancement. These should be treated in the same way Not Use (DU) signal. DU — ...

  • Page 19

    ... Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted ...

  • Page 20

    ... CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU ...

  • Page 21

    ... The confirm command is issued after the data streaming for writing into the buffer is done. This instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP) ...

  • Page 22

    Table 8: Command Codes and Definitions (Sheet Mode Code Device Mode Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Block lock Setup 0x01 Block lock Block Locking/ Unlocking 0xD0 Block Unlock 0x2F Block Lock-Down 0x60 ...

  • Page 23

    P30-65nm 6.2 Device Command Bus Cycles Device operations are initiated by writing specific device commands to the Command User Interface (CUI). Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to ...

  • Page 24

    ... DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device) DnA = Address within the device Identification code address offset. CFI-A = Read CFI address offset Word address of memory location to be written Address within the block. OTP-RA = Protection Register address. LRA = Lock Register address. ...

  • Page 25

    ... AVQV In asynchronous page mode, sixteen data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest four address bits determine which word of the 16- word page is output from the data buffer at any given time ...

  • Page 26

    ... User-Programmable OTP Register Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. BBA = Block Base Address. 2. DBA = Device base Address, Numonyx reserves other configuration address locations. 3. The GPR is used as read out register for Extended Function interface command. Table 11: Device ID codes ID Code Type Device Code Note: The 512-Mbit devices do not have a unique Device ID associated with them ...

  • Page 27

    ... Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see The Status Register can be examined for programming progress and errors by reading at any address ...

  • Page 28

    ... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set ...

  • Page 29

    ... BEFP programs one block at a time; all buffer data must fall within a single block Suspend BEFP cannot be suspended Programming the flash Programming to the flash memory array can occur only when the buffer is full. memory array Note: 1. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly ...

  • Page 30

    ... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 512, the remaining buffer locations must be filled with 0xFFFF ...

  • Page 31

    P30-65nm 8.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device ...

  • Page 32

    Figure 11: Example VPP Supply Connections ≤ 10K Ω • Factory Programming with • Complete write/Erase Protection when PPH • Low Voltage and Factory Programming Datasheet 32 V VCC CC PROT ...

  • Page 33

    ... During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory block array that are ones can be changed to zeros only by programming the block (see “ ...

  • Page 34

    ... Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation read operation within any block except the block that is erase suspended (see Figure 40, “ ...

  • Page 35

    ... Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power- locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. ...

  • Page 36

    Figure 12: Block Locking State Diagram Note: LK: ...

  • Page 37

    ... P30-65nm 10.2 Selectable One-Time Programmable Blocks The OTP security feature on P30-65nm device is backward compatible to the P30- 130nm device. Please see your local Numonyx representative for details about its implementation. 10.3 Password Access The Password Access is a security enhancement offered on the P30-65nm device. This feature protects information stored in array blocks by preventing content alteration or reads until a valid 64-bit password is received ...

  • Page 38

    Registers When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...

  • Page 39

    P30-65nm Table 14: Status Register Description (Sheet Status Register (SR) Program Suspend Status 2 (PSS) 1 Block-Locked Status (BLS) 0 BEFP Status (BWS) Note: Always clear the Status Register prior to resuming erase operations. It avoids Status ...

  • Page 40

    Table 15: Read Configuration Register Description (Sheet 14:11 Latency Count (LC[3:0]) WAIT Polarity (WP Reserved (R) 8 WAIT Delay (WD) Burst Sequence (BS) 7 Clock Edge (CE) 6 5:4 Reserved (R) Burst Wrap (BW) 3 ...

  • Page 41

    P30-65nm Figure 13: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 DQ ...

  • Page 42

    Table 16: LC and Frequency Support Latency Count Settings 5 (TSOP); 4 (Easy BGA) 5 (Easy BGA) Figure 14: Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] A[MAX:1] D[15:0] 11.2.3 End of Word Line (EOWL) Considerations End ...

  • Page 43

    P30-65nm Table 17: End of Wordline Data and WAIT state Comparison Latency Count Data States 1 Not Supported Not Supported ...

  • Page 44

    Table 18: WAIT Functionality Table Condition CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ CE# =’0’, OE# = ‘0’ Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads All Writes Notes: 1. Active: WAIT is ...

  • Page 45

    ... Each OTP register can be individually locked. The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers, Datasheet ...

  • Page 46

    Users can program these registers as needed. Once programmed, users can then lock the OTP Register(s) to prevent additional bit programming (see “OTP Register Map” on page The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR ...

  • Page 47

    ... Bit 0 of Lock Register 0 is already programmed during the manufacturing process by Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1 of Lock Register 0 can be programmed by user to the upper half segment of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘ ...

  • Page 48

    ... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...

  • Page 49

    ... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...

  • Page 50

    Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 21: Parameter Temperature under bias Storage temperature Voltage on any signal ...

  • Page 51

    P30-65nm 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 23: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], WAIT LO Current 256-Mbit Standby, CCS CC I Power-Down ...

  • Page 52

    Table 23: DC Current Characteristics (Sheet Sym Parameter I V Blank Check PPBC PP Notes: 1. All currents are RMS unless noted. Typical values at typical the average current measured over any 5 ...

  • Page 53

    P30-65nm 15.0 AC Characteristics 15.1 AC Test Conditions Figure 18: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst ...

  • Page 54

    Capacitance Table 26: Capacitance Parameter Signals Address, Data, Input CE#, WE#, OE#, Capacitance RST#, CLK, ADV#, WP# Output Data, WAIT Capacitance Notes: 1. Sampled, but not 100% tested. 15.3 AC Read Specifications Table 27: AC Read Specifications (Sheet 1 ...

  • Page 55

    P30-65nm Table 27: AC Read Specifications (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV R104 t ADV# pulse ...

  • Page 56

    Figure 21: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low). Figure 22: Asynchronous Single-Word Read ...

  • Page 57

    ... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Datasheet ...

  • Page 58

    Figure 25: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Notes: 1. WAIT ...

  • Page 59

    P30-65nm 15.4 AC Write Specifications Table 28: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data ...

  • Page 60

    Figure 27: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 28: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] ...

  • Page 61

    P30-65nm Figure 29: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [ WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 30: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address ...

  • Page 62

    Figure 31: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, ...

  • Page 63

    P30-65nm 16.0 Program and Erase Characteristics Table 29: Program and Erase Specifications Num Symbol Parameter Program W200 t Single word PROG/W Time Aligned 32-Word, BP time (32 words) Aligned 64-Wd, BP time (64 words) Program Aligned 128-Wd, BP time W250 ...

  • Page 64

    ... Package Designator -Lead TSOP, lead-free RC = 64- Ball Easy BGA , leaded Ball Easy BGA, lead-free Product Line Designator 28F = Numonyx™ Flash Memory Device Density 256 = 256- Mbit Note: The last digit is randomly assigned to cover packing media and/or features or other specific configuration ...

  • Page 65

    ... SCSP Products Figure 33: Decoder for SCSP P30-65nm Package Designator RD = Numonyx™ SCSP, leaded PF = Numonyx™ SCSP, lead - free RC = 64- Ball Easy BGA , leaded PC = 64- Ball Easy BGA, lead - free Product Designator 48F = Numonyx™ Flash Memory Only Device Density die ...

  • Page 66

    Appendix A Supplemental Reference Information A.1 Common Flash Interface Tables The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read ...

  • Page 67

    ... BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord). 3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended CFI Table. A.1.3 Read CFI Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...

  • Page 68

    Table 35: CFI Identification Offset Length 10h 3 Query-unique ASCII string “QRY“ 13h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms 15h 2 Extended Query Table primary algorithm address 17h 2 Alternate ...

  • Page 69

    P30-65nm A.1.4 Device Geometry Definition Table 36: System Interface Information Offset Length VCC logic supply minimum program/erase voltage 1Bh 1 VCC logic supply maximum program/erase voltage 1Ch 1 VPP [programming] supply minimum program/erase voltage 1Dh 1 VPP [programming] supply maximum ...

  • Page 70

    Table 37: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device w idth capabilities as described in ...

  • Page 71

    ... P30-65nm A.1.5 Numonyx-Specific Extended CFI Table Table 38: Primary Vendor-Specific Extended CFI Offset (1) Length P = 10Ah (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 11– ...

  • Page 72

    Table 39: Protection Register Information Offset (1) Length P = 10Ah (P+E)h 1 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description (P+10)h This field ...

  • Page 73

    P30-65nm Figure 34: Burst Read Information (1) Offset Length P = 10Ah (P+1D)h 1 Page Mode Read capability bits 0–7 = “n” such that 2 read-page bytes. See offset 28h for device w ord w idth to determine page-mode data ...

  • Page 74

    Table 41: Partition Region 1 Information Offset ( 10Ah Bottom Top (P+24)h (P+24)h Data size of this Parition Region Information field (P+25)h (P+25)h (# addressable locations, including this field) (P+26)h (P+26)h Number of identical partitions w ithin the ...

  • Page 75

    P30-65nm Table 42: Partition Region 1 Information (continued) Offset ( 10Ah Bottom Top (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0– y identical-size erase blks in a partition ...

  • Page 76

    Table 43: Partition and Erase Block Region Information Partition and Erase-block Region Information Address 12D: 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A 13B: 13C: 13D: 13E: 13F: 140: 141: 142: 143: 144: 145: 146: ...

  • Page 77

    ... Bits 0–9 = Address offset (w ithin 32Mbit segment) of referenced CFI table (P+4A)h Bits 10–27 = nth 32Mbit segment of referenced CFI table (P+4B)h Bits 28–30 = Memory Type Bit 31 = Another CFI Link field immediately follow s (P+4C)h 1 CFI Link Field Quantity Subfield definitions Bits 0–3 = Quantity field (n such that n+1 equals quantity) Bit 4 = Table & ...

  • Page 78

    A.2 Flowcharts Figure 35: Word Program Flowchart Start Command Cycle - Issue Program Command - Address = location to program - Data = 0x40 Data Cycle - Address = location to program - Data = Data to program Check Ready ...

  • Page 79

    P30-65nm Figure 36: Program Suspend/Resume Flowchart Start Read Status Write 70h Any Address Program Suspend Write B0h Any Address Read Status Register Read Array Write FFh Any Address Read Array ...

  • Page 80

    Figure 37: Buffer Program Flowchart Start Device No Supports Buffer Writes ? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read Status Register Block Address (note 7) Is WSM ...

  • Page 81

    P30-65nm Figure 38: BEFP Flowchart Setup Phase Start Issue BEFP Setup Cmd (Data = 0x80) Issue BEFP Confirm Cmd (Data = 00D0h) BEFP Setup Delay Read Status Register Yes (SR.7=0) BEFP Setup Done ? No (SR.7=1) SR Error Handler (User-Defined) ...

  • Page 82

    Figure 39: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase ...

  • Page 83

    P30-65nm Figure 40: Erase Suspend/Resume Flowchart Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register Read Program Read or Program? Read Array No ...

  • Page 84

    Figure 41: Block Lock Operations Flowchart Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change ? Yes Read Array Write FFh ...

  • Page 85

    P30-65nm Figure 42: Protection Register Programming Flowchart Datasheet 85 Start OTP Program Setup - Write 0xC0 - OTP Address Confirm Data - Write OTP Address and Data Check Ready Status - Read Status Register Command not required - Perform read ...

  • Page 86

    Figure 43: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear ...

  • Page 87

    P30-65nm A.3 Write State Machine The Next State Table shows the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read ...

  • Page 88

    Table 45: Next State Table for P30-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) Setup (8) BP Load 1 (8) BP Load 2 BP Confirm Ready (Error [Botch]) Buffer Pgm ...

  • Page 89

    P30-65nm Table 45: Next State Table for P30-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) EFI Setup Sub-function Setup Sub-op-code Load 1 Sub-function Sub-function Confirm in Erase Suspend if data load in ...

  • Page 90

    Table 46: Output Next State Table for P30-65nm Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Setup, Load 1, Load 2 BP Setup, ...

  • Page 91

    P30-65nm Appendix B Conventions - Additional Information B.1 Conventions VCC: Signal or voltage connection V : Signal or voltage level CC 0x: Hexadecimal number prefix h: Hexadecimal number suffix 0b: Binary number prefix SR.4: Denotes an individual register bit. A[15:0]: ...

  • Page 92

    ... Bottom parameter device : Datasheet 92 A group of bits, bytes, or words within the flash memory array that erase simultaneously. The P30-65nm has two block sizes: 32 KByte and 128 KByte. An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. ...

  • Page 93

    ... Remove 128M related contents; Return to StrataFlash trademark; Update the buffer program for cross 512-Word boundary; Correct A24 to A25 for virtual CE description in section 1.3; Remove Numonyx Confidential. Update Buffer program flowchart same as 130nm; Minor wording modifications. Update new trademark Axcell; Remove 64M related contents. ...

  • Page 94

    Revision Date Revision May 2008 01 Datasheet 94 Description Initial Release P30-65nm Mar 2010 Order Number: 320002-10 ...