RC28F256P30BFA NUMONYX, RC28F256P30BFA Datasheet - Page 21

IC FLASH 256MBIT 100NS 64EZBGA

RC28F256P30BFA

Manufacturer Part Number
RC28F256P30BFA
Description
IC FLASH 256MBIT 100NS 64EZBGA
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet

Specifications of RC28F256P30BFA

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
256M (16Mx16)
Speed
100ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-EZBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
898885
898885
RC28F256P30BF 898885

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P30-65nm
6.0
6.1
Table 8:
Datasheet
21
Mode
Write
Erase
Read
Command Codes and Definitions (Sheet 1 of 2)
Command Set
Device Command Codes
The system CPU provides control of all in-system read, write, and erase operations of
the device via the system bus. The on-chip Write State Machine (WSM) manages all
block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
Code
0xD0
0xD0
0xD0
0x70
0x90
0x98
0x50
0x40
0xE8
0x80
0x20
0xFF
Read Array
Read Status
Register
Read Device ID
or Read
Configuration
Register (RCR)
Read CFI
Clear Status
Register
Word Program
Setup
Buffered Program
Buffered Program
Confirm
BEFP Setup
BEFP Confirm
Block Erase Setup
Block Erase Confirm
Device Mode
Places the device in Read Array mode. Array data is output on DQ[15:0].
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. Status Register data is output
on DQ[7:0].
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or Protection Register data on DQ[15:0].
Places the device in Read CFI mode. Subsequent reads output Common Flash
Interface information on DQ[7:0].
The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the Status Register Data for synchronous Non-array reads. The Read
Array command must be issued to read array data after programming has
finished.
This command loads a variable number of words up to the buffer size of 512
words onto the program buffer.
The confirm command is issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory
Program mode (BEFP). The CUI then waits for the BEFP Confirm command,
0xD0, that initiates the BEFP algorithm. All other commands are ignored
when BEFP mode begins.
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR.4 and SR.5, and
places the device in read status register mode.
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array reads.
Description
Order Number: 320002-10
Mar 2010

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