RC28F256P30BFA NUMONYX, RC28F256P30BFA Datasheet - Page 28

• Manufacturer Part Number: RC28F256P30BFA
• Description: IC FLASH 256MBIT 100NS 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of RC28F256P30BFA

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 898885; 898885; RC28F256P30BF 898885

Note:
8.3
Datasheet
28
CE# and OE# low drive device to update Status Register. It is not allowed to issue 70h to read
SR data after E8h command otherwise 70h would be counted as Word Count.
The device default state is to output SR data after the Buffer Programming Setup Command.
When the Buffered Programming Setup command is issued (see
“Command Set” on page
availability of the buffer. SR.7 indicates buffer availability: if set, the buffer is available;
if cleared, the buffer is not available.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy
BGA and TSOP, A[8:0] for QUAD+ package). The maximum buffer size would be 256-
word if the misaligned address range is crossing a 512-word boundary during
programming.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the
array, the device stops programming, and Status Register bits SR[7,4] are set,
indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with V
(see
the device with V
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while V
bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see
Flowchart” on page
across 512 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
Section 13.2, “Operating Conditions” on page 50
PP
= V
81). It uses a write buffer to spread MLC program performance
PPH
21), Status Register information is updated and reflects the
).
PP
is at or below V
for limitations when operating
PPLK
Section 6.0,
Order Number: 320002-10
, Status Register
PP
Figure 38, “BEFP
= V
PPL
P30-65nm
or V
Mar 2010
PPH