IC FLASH 128MBIT 85NS 64EZBGA

 

RC28F128P30B85A

Manufacturer Part NumberRC28F128P30B85A
DescriptionIC FLASH 128MBIT 85NS 64EZBGA
ManufacturerNUMONYX
SeriesStrataFlash™
RC28F128P30B85A datasheets

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Specifications of RC28F128P30B85A

Format - MemoryFLASHMemory TypeFLASH
Memory Size128M (8Mx16)Speed85ns
InterfaceParallelVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case64-TBGA
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names873868
873868
RC28F128P30B85
RC28F128P30B85 873868
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P30
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while V
SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
8.4
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see
Flowchart” on page
across 32 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 32 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR[0] indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 32-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
8.4.1
BEFP Requirements and Considerations
Table 15: BEFP Requirements
Parameter/Issue
°
Case Temperature
T
= 25
C ± 5 °C
C
V
Within operating range
CC
VPP
Driven to V
PPH
Setup and Confirm
Target block unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) of the block to be programmed must be held constant
Programming
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired
Buffer Alignment
WA0 must align with the start of an array buffer boundary
Note:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =
0x00.
August 2008
Order Number: 306666-12
is below V
PP
83). It uses a write buffer to spread MLC program performance
Requirement
, Status Register bits
PPLK
Figure 37, “BEFP
Notes
1
Datasheet
31

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