- Components/
- Integrated Circuits (ICs)/
- Memory/
RC28F128P30B85A
RC28F128P30B85A | |
|---|---|
| Manufacturer Part Number | RC28F128P30B85A |
| Description | IC FLASH 128MBIT 85NS 64EZBGA |
| Manufacturer | NUMONYX |
| Series | StrataFlash™ |
| RC28F128P30B85A datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of RC28F128P30B85A | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 128M (8Mx16) | Speed | 85ns |
| Interface | Parallel | Voltage - Supply | 1.7 V ~ 2 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 64-TBGA |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 873868 873868 RC28F128P30B85 RC28F128P30B85 873868 |
PrevNext
P30
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR[0] = 0 and the device is ready for the
next buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program is
proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.4.4
BEFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
8.5
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation (see
page
81).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. V
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.6
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see
Resume Flowchart” on page
August 2008
Order Number: 306666-12
Figure 35, “Program Suspend/Resume Flowchart” on
Section 16.0, “Program and Erase Characteristics” on page
must remain at its programming level, and WP# must remain
PP
81).
67.
Figure 35, “Program Suspend/
Datasheet
33
Related parts for RC28F128P30B85A | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
|
|
IC FLASH 128MBIT 65NM 64EZBGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 85NS 64EZBGA | NUMONYX | |
|
|
IC FLASH 128MBIT 85NS 64EZBGA | NUMONYX | |
|
|
IC FLASH 128MBIT 65NM 64EZBGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 85NS 64EZBGA | NUMONYX |
|
|
|
Numonyx StrataFlash Embedded Memory | NUMONYX [Numonyx B.V] |
|
|
|
Numonyx Axcell | Numonyx |
|
|
|
Numonyx Axcell Tm P33-65nm Flash Memory 128-mbit, 64-mbit Single Bit Per Cell Sbc | Numonyx |
|
|
|
IC FLASH 128MBIT 25NS 64BGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 25NS 64BGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 75NS 64EZBGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 75NS 64EZBGA | NUMONYX |
|
|
|
IC FLASH 128MBIT 75NS 64EZBGA | NUMONYX |
|
|
|
PARALLEL NOR | NUMONYX | |
|
|
Numonyx B.V |
|
|

