IC FLASH 128MBIT 85NS 64EZBGA

 

RC28F128P30B85A

Manufacturer Part NumberRC28F128P30B85A
DescriptionIC FLASH 128MBIT 85NS 64EZBGA
ManufacturerNUMONYX
SeriesStrataFlash™
RC28F128P30B85A datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of RC28F128P30B85A

Format - MemoryFLASHMemory TypeFLASH
Memory Size128M (8Mx16)Speed85ns
InterfaceParallelVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case64-TBGA
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names873868
873868
RC28F128P30B85
RC28F128P30B85 873868
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Page 50/97

Download datasheet (2Mb)Embed
PrevNext
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
and V
should attain their minimum operating voltage before applying V
CC
CCQ
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 23: Reset Specifications
Num
Symbol
P1
t
RST# pulse width low
PLPH
RST# low to device reset during erase
P2
t
PLRH
RST# low to device reset during program
V
Power valid to RST# de-assertion (high) 130nm
CC
P3
t
VCCPH
V
Power valid to RST# de-assertion (high) 65nm
CC
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if t
is < t
PLPH
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
When RST# is tied to the V
CC
6.
When RST# is tied to the V
CCQ
7.
Reset completes within t
if RST# is asserted while no erase or program operation is executing.
PLPH
Datasheet
50
Parameter
, but this is not guaranteed.
PLPH MIN
supply, device will not be ready until t
VCCPH
supply, device will not be ready until t
VCCPH
Min
Max
Unit
100
-
ns
-
25
-
25
µs
60
-
300
-
after V
≥ V
.
CC
CCMIN
after V
≥ V
.
CC
CCMIN
August 2008
P30
.
PP
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
1,4,5,6
306666-12