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RC28F128P30B85A
RC28F128P30B85A | |
|---|---|
| Manufacturer Part Number | RC28F128P30B85A |
| Description | IC FLASH 128MBIT 85NS 64EZBGA |
| Manufacturer | NUMONYX |
| Series | StrataFlash™ |
| RC28F128P30B85A datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of RC28F128P30B85A | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 128M (8Mx16) | Speed | 85ns |
| Interface | Parallel | Voltage - Supply | 1.7 V ~ 2 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 64-TBGA |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 873868 873868 RC28F128P30B85 RC28F128P30B85 873868 |
PrevNext
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
and V
should attain their minimum operating voltage before applying V
CC
CCQ
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 23: Reset Specifications
Num
Symbol
P1
t
RST# pulse width low
PLPH
RST# low to device reset during erase
P2
t
PLRH
RST# low to device reset during program
V
Power valid to RST# de-assertion (high) 130nm
CC
P3
t
VCCPH
V
Power valid to RST# de-assertion (high) 65nm
CC
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if t
is < t
PLPH
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
When RST# is tied to the V
CC
6.
When RST# is tied to the V
CCQ
7.
Reset completes within t
if RST# is asserted while no erase or program operation is executing.
PLPH
Datasheet
50
Parameter
, but this is not guaranteed.
PLPH MIN
supply, device will not be ready until t
VCCPH
supply, device will not be ready until t
VCCPH
Min
Max
Unit
100
-
ns
-
25
-
25
µs
60
-
300
-
after V
≥ V
.
CC
CCMIN
after V
≥ V
.
CC
CCMIN
August 2008
P30
.
PP
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
1,4,5,6
306666-12
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