PC48F4400P0VB0EA

Manufacturer Part NumberPC48F4400P0VB0EA
DescriptionIC FLASH 512MBIT 65NM 64EZBGA
ManufacturerNUMONYX
SeriesAxcell™
PC48F4400P0VB0EA datasheets

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Specifications of PC48F4400P0VB0EA

Format - MemoryFLASHMemory TypeFLASH
Memory Size512M (32Mx16)Speed100ns
InterfaceParallelVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case64-TBGA
Package64EZBGACell TypeNOR
Density512 MbArchitectureSectored
Block OrganizationAsymmetricalLocation Of Boot BlockBottom
Typical Operating Supply Voltage1.8 VSector Size32KByte x 4|128KByte x 511
Timing TypeAsynchronous|SynchronousInterface TypeParallel|Serial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
PF48F4000P0ZBQEF PDF datasheetRD48F4400P0VBQEJ PDF datasheet #2
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P30-65nm
Table 5:
TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol
Type
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
RFU
—
enhancement. These should be treated in the same way as a Do Not Use (DU) signal.
DU
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
NC
—
NO CONNECT: No internal connection; can be driven or floated.
Table 6:
QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)
Symbol
Type
ADDRESS INPUTS: Device address inputs. 256-Mbit: A[23:0]; 512-Mbit: A[24:0]. Note: The
A[MAX:0]
Input
virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is
accomplished by setting A24 high (V
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
Input/
DQ[15:0]
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
Output
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
Flash CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
F1-CE#
Input
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be driven high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
CLK
Input
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
F1-OE#
Input
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
RST#
Input
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR.10, WT) determines its polarity when asserted. WAIT’s active output is V
V
when CE# and OE# are V
OH
WAIT
Output
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
WE#
Input
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
WP#
Input
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V
voltages should not be attempted.
Set V
= V
PP
Power/
VPP
from the system supply, the V
lnput
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Datasheet
17
Name and Function
Name and Function
).
IH
. WAIT is high-Z if CE# or OE# is V
IL
≤ V
PP
PPLK
for in-system program and erase operations. To accommodate resistor or diode drops
PPL
level of V
can be as low as V
IH
PP
.
IH
. Block erase and program at invalid V
PP
min. V
must remain above V
PPL
PP
Mar 2010
Order Number: 320002-10
or
OL
PPL

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