PCF85176T/1,118 NXP Semiconductors, PCF85176T/1,118 Datasheet
PCF85176T/1,118
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PCF85176T/1,118
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PCF85176T/1,118 Summary of contents
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PCF85176 Universal LCD driver for low multiplex rates Rev. 01 — 14 April 2010 1. General description The PCF85176 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number PCF85176H PCF85176T 4. Marking Table 2. Type number PCF85176H PCF85176T 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85176 PCF85176_1 Product data sheet ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF85176_1 Product data sheet n. S34 3 S35 S36 4 S37 5 S38 6 7 S39 8 n.c. n.c. 9 SDA 10 SCL 11 12 SYNC 13 CLK OSC Top view. For mechanical details, see Pinning diagram for TQFP64 (PCF85176H) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Fig 3. PCF85176_1 Product data sheet 1 BP2 2 BP1 BP3 S10 14 PCF85176T S11 15 16 S12 17 S13 S14 18 S15 19 S16 20 21 S17 22 S18 S19 23 S20 24 S21 25 26 S22 27 S23 S24 28 Top view. For mechanical details, see Pinning diagram for TSSOP56 (PCF85176T) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL CLK V DD SYNC OSC SA0 LCD BP0, BP2, BP1, BP3 S0 to S39 47, n.c. PCF85176_1 Product data sheet Pin description Pin TQFP64 TSSOP56 (PCF85176H) (PCF85176T 56 64 24, - 33, 48 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7. Functional description The PCF85176 is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCF85176 depend on the number of active backplane outputs required ...
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... NXP Semiconductors • Display is disabled Remark: Do not transfer data on the I the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between V switch if the 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration ...
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... NXP Semiconductors The RMS off-state voltage ( off RMS Discrimination is the ratio ---------------------- - V off RMS Using Equation ⁄ 1 bias is 2 ⁄ 1 bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Fig 5. PCF85176_1 Product data sheet V LCD ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85176 allows the use of Figure 7. Fig 6. PCF85176_1 Product data sheet ⁄ bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD V SS ...
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... NXP Semiconductors Fig 7. PCF85176_1 Product data sheet V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD LCD 2V /3 LCD LCD LCD 2V /3 LCD S n LCD LCD 2V /3 LCD V /3 LCD state − LCD − LCD − V LCD V LCD ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Fig 8. PCF85176_1 Product data sheet Figure 8. V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD V SS ...
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... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 9. PCF85176_1 Product data sheet Figure 9. V LCD 2V /3 LCD V /3 LCD ...
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... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF85176 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF85176 in the system that are connected in cascade. ...
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... NXP Semiconductors • In static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 40 × 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors The following applies to • In static drive mode the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...
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... NXP Semiconductors The hardware subaddress must not be changed while the device is being accessed on the 2 I C-bus interface. 7.13 Output bank selector The output bank selector (see address for transfer to the display register. The actual row selected depends on the selected LCD drive mode in operation and on the instant in the multiplex sequence. ...
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... NXP Semiconductors Table 6. Blink mode off [1] The blink frequency is proportional to the clock frequency (f Table The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see 7 ...
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... NXP Semiconductors SDA SCL Fig 13. Definition of START and STOP conditions 7.16.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see ...
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... NXP Semiconductors Fig 15. Acknowledgement of the I 2 7.16.5 I C-bus controller The PCF85176 acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are ...
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... NXP Semiconductors • PCF85176 for very large LCD applications • The use of two types of LCD multiplex drive 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF85176 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCF85176 whose SA0 inputs are set to the alternative level ...
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... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF85176 are defined in Table 8. Bit position labelled not used. Command Bit mode-set load-data-pointer device-select bank-select blink-select All available commands carry a continuation bit C in their most significant bit position as shown in transfer to arrive will also represent a command ...
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... NXP Semiconductors Table 11. Bit Table 12. Bit Table 13. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 14. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. ...
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... NXP Semiconductors 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. ...
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... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD DD(LCD tot ...
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... NXP Semiconductors 10. Static characteristics Table 16. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V power-on reset supply voltage P(POR) V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors Fig 19. Typical I Fig 20. Typical I PCF85176_1 Product data sheet (μ °C; 1:4 multiplex 6 amb LCD 2 display connected; I C-bus inactive. with respect DD(LCD) (μ °C; 1:4 multiplex 1.536 kHz; all RAM written with logic 1; no display connected. amb clk(ext) with respect to V DD(LCD) All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 11. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) f frame frequency fr t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay ...
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... NXP Semiconductors BPn, Sn Fig 21. Driver timing waveforms SDA SCL SDA Fig 22. I PCF85176_1 Product data sheet clk t clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation Large display configurations PCF85176 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster 1 2 When cascaded PCF85176 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... NXP Semiconductors V LCD V DD PROCESSOR/ CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 23. Cascaded PCF85176 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF85176. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e ...
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... NXP Semiconductors Table 19. Number of devices The PCF85176 can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. synchronization signals cascaded configuration only one PCF85176 master must be used as clock source. All other PCF85176 in the cascade must be configured as slave such that they receive the clock from the master ...
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... NXP Semiconductors Fig 24. Synchronization of the cascade for the various PCF85176 drive modes PCF85176_1 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode ...
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... NXP Semiconductors 13. Package outline TQFP64: plastic thin quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC ...
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... NXP Semiconductors TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15 ...
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... NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 22. Acronym CMOS CDM DC HBM LCD LSB MM MSB MSL PCB POR RAM RC RMS SCL SDA ...
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... NXP Semiconductors 17. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-On Reset (POR 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms ...