PCF85132U/2DA/1,02 NXP Semiconductors, PCF85132U/2DA/1,02 Datasheet
PCF85132U/2DA/1,02
Specifications of PCF85132U/2DA/1,02
Related parts for PCF85132U/2DA/1,02
PCF85132U/2DA/1,02 Summary of contents
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PCF85132 LCD driver for low multiplex rates Rev. 1 — 23 November 2010 1. General description The PCF85132 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and up ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number PCF85132U 4. Marking Table 2. Type number PCF85132U PCF85132 Product data sheet Ordering information Package Name Description PCF85132U bare die; 197 bumps; 6.5 × 1.16 × 0.40 mm Marking codes All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85132 PCF85132 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCF85132 ...
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Pinning information 6.1 Pinning PCF85132 Viewed from active side. For mechanical details, see Fig 2. Pinning diagram of PCF85132 + Figure 32 on page 44. 013aaa361 ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDAACK [1] SDA SCL CLK V DD SYNC OSC T1, T2, and T3 A0 and A1 SA0 [ LCD BP2 and BP0 S0 to S79 BP0, BP2, BP1, and BP3 S80 to S159 BP3 and BP1 [1] For most applications SDA and SDAACK are shorted together (see ...
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... NXP Semiconductors 7. Functional description The PCF85132 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure backplanes and up to 160 segments. The display configurations possible with the PCF85132 depend on the required number of active backplane outputs ...
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... NXP Semiconductors Fig 4. The host microprocessor or microcontroller maintains the 2-line I channel with the PCF85132. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to V power supplies (V 7 ...
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... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of ...
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... NXP Semiconductors Using Equation ⁄ 1 bias is 2 ⁄ 1 bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V 7.3.1 Electro-optical performance Suitable values for V RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel ...
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... NXP Semiconductors Fig 5. PCF85132 Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2010 PCF85132 LCD driver for low multiplex rates V [V] V RMS low high GREY ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 6. PCF85132 Product data sheet V LCD BP0 V SS ...
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... NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85132 allows the use of Figure 8. Fig 7. PCF85132 Product data sheet ⁄ bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD V SS ...
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... NXP Semiconductors Fig 8. PCF85132 Product data sheet V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD LCD 2V /3 LCD LCD LCD 2V /3 LCD S n LCD LCD 2V /3 LCD V /3 LCD state − LCD − LCD − V LCD V LCD ...
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... NXP Semiconductors 7.4.3 1:3 multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Fig 9. PCF85132 Product data sheet Figure 9. V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD V SS ...
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... NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 10. Waveforms for the 1:4 multiplex drive mode with PCF85132 Product data sheet Figure 10 ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85132 are timed by a frequency f which either is derived from the built-in oscillator frequency clk or equals an external clock frequency clk Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD state, which is not suitable for the liquid crystal ...
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... NXP Semiconductors 7.8 Segment outputs The LCD drive section includes 160 segment outputs (S0 to S159) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display register. When less than 160 segment outputs are required the unused segment outputs must be left open-circuit ...
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... NXP Semiconductors Fig 11. Display RAM bitmap When display data is transmitted to the PCF85132 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the ...
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... NXP Semiconductors The PCF85132 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled ...
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... NXP Semiconductors 7.16 Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL Fig 14. Definition of START and STOP conditions 7.16.2 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in ...
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... NXP Semiconductors Fig 16. Acknowledgement on the I 2 7.16.4 I C-bus controller The PCF85132 acts transmit data the acknowledge signals from the selected devices. Device selection depends on the 2 I C-bus slave address, on the transferred command data, and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0 and A1 are normally tied to V which defines the hardware subaddress 0 ...
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... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF85132 with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCF85132 with the alternative SA0 level ignore the whole I R slave address control byte EXAMPLES ...
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... NXP Semiconductors In this way it is possible to configure the device and then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCF85132 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter ...
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... NXP Semiconductors Table 11. Bit [1] Power-on and reset value. Table 12. Bit [1] Power-on and reset value. Table 13. Bit [1] Power-on and reset value. Table 14. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [2] Power-on and reset value. PCF85132 Product data sheet ...
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... NXP Semiconductors Table 15. Bit [1] Power-on and reset value. [2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. Table 16. Bit [1] Nominal frame frequency calculated for an internal operating frequency of 1.800 kHz. ...
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... NXP Semiconductors 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF85132 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. ...
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... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 17. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD I DD(LCD tot ...
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... NXP Semiconductors 10. Static characteristics Table 18. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V input voltage I V HIGH-level input voltage IH V LOW-level input voltage IL V output voltage O V HIGH-level output voltage on pin SYNC, CLK ...
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... NXP Semiconductors Table 18. Static characteristics Symbol Parameter LCD outputs ΔV output voltage variation O R output resistance O [1] LCD outputs are open-circuit; inputs at V [2] External clock with 50 % duty factor. [3] For typical values, see Figure 20. [4] For typical values, see Figure 21. ...
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... NXP Semiconductors I DD(LCD) (μA) Fig 21. I PCF85132 Product data sheet °C; 1:4 multiplex; all RAM written with logic 1; no display connected amb with respect to V DD(LCD) LCD All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2010 PCF85132 LCD driver for low multiplex rates ...
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... NXP Semiconductors 11. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter f clock frequency clk f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Δf frame frequency variation fr t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay ...
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... NXP Semiconductors (Hz) Fig 22. Typical clock frequency (f Fig 23. Frame frequency variation PCF85132 Product data sheet 1860 f clk 1820 1780 1740 1700 °C. T amb ) with respect to voltage clk (Hz −60 −40 − ± 0.5 V; frame-frequency-prescaler = 011 typical. Condition The frame frequency ( calculated from the clock frequency (f ...
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... NXP Semiconductors BP0 to BP3, and S0 to S159 Fig 24. Driver timing waveforms SDA SCL HD;STA clock cycle SDA t SU;STA SCL Sr 2 Fig 25. I C-bus timing waveforms when SDA and SDAACK are connected PCF85132 Product data sheet clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv ...
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... NXP Semiconductors 12. Application information 12.1 Pull-up resistor sizing on I 12.1.1 Max value of pull-up resistor The bus capacitance (C capacitance on pin SDA limits the maximum value of the pull-up resistor (R specified rise time. According to the I input threshold will be calculated with whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are ...
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... NXP Semiconductors R PU(max) (kΩ) Fig 26. Values for R R PU(min) (kΩ) Fig 27. Values for R 12.2 SDA and SDAACK configuration The Serial DAta line (SDA) and the I lines can be connected together to facilitate a single line SDA. Fig 28. SDA, SDAACK configurations PCF85132 Product data sheet ...
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... NXP Semiconductors 12.3 Cascaded operation In large display configurations PCF85132 can be distinguished on the same 2 I C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable 2 I C-bus slave address (SA0). Table 20. Cluster 1 2 When cascaded PCF85132 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... NXP Semiconductors Table 21. Number of devices the cascaded applications, the OSC pin of the PCF85132 with subaddress 0 is connected to V the CLK pin. The other PCF85132 devices are having the OSC pin connected to V meaning that these devices are ready to receive external clock, the signal being provided by the device with subaddress 0 ...
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... NXP Semiconductors V LCD V DD PROCESSOR/ CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 29. Cascaded configuration with two PCF85132 using the internal clock of the master PCF85132 Product data sheet SYNC t r ≤ SDA HOST MICRO- SCL SYNC ...
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... NXP Semiconductors V LCD V DD PROCESSOR/ CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 30. Cascaded configuration with one PCF85132 and one PCF85133 using the internal PCF85132 Product data sheet SYNC t r ≤ SDA HOST MICRO- SCL SYNC ...
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... NXP Semiconductors Fig 31. Synchronization of the cascade for the various PCF85132 drive modes PCF85132 Product data sheet = BP0 SYNC (a) static drive mode BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1:2 multiplex drive mode BP2 (1/3 bias) SYNC (c) 1:3 multiplex drive mode BP3 ...
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... NXP Semiconductors 13. Bare die outline Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm 166 C1 Marking code: PC85132/232-1 167 e Dimensions (1) (1) (1) Unit max 0.018 mm nom 0.40 0.015 0.380 0.0338 min 0.012 Note 1. Dimension not drawn to scale. Outline version IEC PCF85132U Fig 32. Bare die outline of PCF85132 ...
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... NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol SDAACK SDAACK SDAACK SDA SDA SDA SCL SCL SCL CLK SYNC OSC SA0 LCD V LCD V LCD BP2 BP0 PCF85132 Product data sheet ...
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... NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 ...
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... NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 ...
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... NXP Semiconductors Fig 33. Alignment marks PCF85132 Product data sheet REF S1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2010 PCF85132 LCD driver for low multiplex rates REF C1 001aah849 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 14. Packing information Table 25. Symbol Fig 34. Tray details PCF85132 Product data sheet Tray dimensions (see Figure 34) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction ...
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... NXP Semiconductors Fig 35. Tray alignment 15. Abbreviations Table 26. Acronym COG DC HBM ITO LCD LSB MM MSB POR RC RAM RMS SCL SDA PCF85132 Product data sheet Abbreviations Description Chip-On-Glass Direct Current Human Body Model Integrated Circuit Inter-Integrated Circuit Indium Tin Oxide Liquid Crystal Display ...
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... NXP Semiconductors 16. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10706 — Handling bare die [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] JESD22-A114 — ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-On Reset (POR 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.3.1 Electro-optical performance ...