ISL80103IRAJZ-T Intersil, ISL80103IRAJZ-T Datasheet - Page 13

• Manufacturer Part Number: ISL80103IRAJZ-T
• Description: IC REG LDO ADJ 3A 10DFN
• Manufacturer: Intersil

Specifications of ISL80103IRAJZ-T

• Regulator Topology: Positive Adjustable
• Voltage - Output: 0.8 V ~ 5 V
• Voltage - Input: 2.2 V ~ 6 V
• Voltage - Dropout (typical): 0.12V @ 3A
• Number Of Regulators: 1
• Current - Output: 3A (Max)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-VFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -

Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10µF or larger ceramic capacitor.
Applications using the ADJ versions, may see improved
performance with the addition of a small ceramic capacitor C
as shown in Figure 2 on page 3. The conditions where C
be beneficial are: (1) V
AC voltage regulation band.
C
results in increasing the bandwidth of the LDO. Typical R3 x C
should be 4μs.
C
Current Limit Protection
The ISL80102, ISL80103 family of LDOs incorporates protection
against overcurrent due to short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 4. If the short or
overload condition is removed from V
to normal voltage mode regulation. In the event of an overload
condition, the LDO might begin to cycle on and off due to the die
temperature exceeding the thermal fault condition. The
TO220/TO263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if the
heatsink of this larger package can keep the die temperature
below the specified typical thermal shutdown temperature.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 10)” on page 4.
The power dissipation can be calculated by using Equation 3:
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
P
PB
PB
D
=
introduces phase lead with the product of R
not recommended for V
(
V
IN
–
V
OUT
)
×
I
OUT
OUT
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
+
V
> 1.5V, (2) C
IN
OUT
×
13
For information regarding Intersil Corporation and its products, see
I
GND
< 1.5V.
OUT
in the quality certifications found at
OUT
, then the output returns
For additional products, see
= 10µF, and (3) tight
ISL80102, ISL80103
3
and C
PB
PB
may
that
(EQ. 3)
PB
PB
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www.intersil.com/design/quality
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
maximum allowable power dissipation as shown in Equation 4:
Where θ
For safe operation, please make sure that power dissipation
calculated in Equation 3, P
allowable power dissipation P
The DFN package uses the copper area on the PCB as a heat-
sink. The EPAD of this package must be soldered to the copper
plane (GND plane) for heat sinking. Figure 40 shows a curve for
the θ
Thermal Fault Protection
In the event the die temperature exceeds typically +160°C, then
the output of the LDO will shut down until the die temperature
can cool down to typically +145°C. The level of power combined
with the thermal impedance of the package (+48°C/W for DFN)
will determine if the junction temperature exceeds the thermal
shutdown temperature.
P
D MAX
FIGURE 40. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
(
46
44
42
40
38
36
34
JA
)
of the DFN package for different copper area sizes.
2
JA
=
is the junction-to-ambient thermal resistance.
(
T
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
4
J MAX
THERMAL VIAS θ
AREA ON PCB
(
6
)
www.intersil.com
–
T
8
A
) θ
⁄
10
D
JA
be less than the maximum
D(MAX)
JA
12
vs EPAD-MOUNT COPPER LAND
14
.
16
A(MAX)
J(MAX)
18
will determine the
20
and the
2
March 24, 2011
22
FN6660.2
(EQ. 4)
24