ISL6334ACRZR5368 Intersil, ISL6334ACRZR5368 Datasheet

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ISL6334ACRZR5368

Manufacturer Part Number
ISL6334ACRZR5368
Description
IC CTRLR PWM 4PHASE BUCK 40QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6334ACRZR5368

Applications
Controller, Intel VR11.1
Voltage - Input
3 V ~ 12 V
Number Of Outputs
1
Voltage - Output
0.5 V ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
VR11.1, 4-Phase PWM Controller with
Light Load Efficiency Enhancement and
Load Current Monitoring Features
The ISL6334AR5368 controls microprocessor core voltage
regulation by driving up to 4 interleaved synchronous-rectified
buck channels in parallel. This multiphase architecture results
in multiplying channel ripple frequency and reducing input and
output ripple currents. Lower ripple results in fewer
components, lower cost, reduced power dissipation, and
smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates and requires high efficiency at light
load. The ISL6334AR5368 utilizes Intersil’s proprietary
Active Pulse Positioning (APP), Adaptive Phase Alignment
(APA) modulation scheme, active phase adding and
dropping to achieve and maintain the extremely fast
transient response with fewer output capacitors and high
efficiency from light to full load.
The ISL6334AR5368 is designed to be completely compliant
with Intel VR11.1 specifications. It accurately reports the load
current via IMON pin to the microprocessor, which sends an
active low PSI# signal to the controller at low power mode.
The controller then enters 1- or 2-phase operation with diode
emulation option to reduce magnetic core and switching
losses, yielding high efficiency at light load. After the PSI#
signal is de-asserted, the dropped phase(s) are added back
to sustain heavy load transient response and efficiency.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The
ISL6334AR5368 senses the output current continuously by
utilizing patented techniques to measure the voltage across the
dedicated current sense resistor or the DCR of the output
inductor. The sensed current flows out of FB pin to develop the
precision voltage drop across the feedback resistor for droop
control. Current sensing circuits also provide the needed
signals for channel-current balancing, average overcurrent
protection and individual phase current limiting. An NTC
thermistor’s temperature is sensed via TM pin and internally
digitized for thermal monitoring and for integrated thermal
compensation of the current sense elements.
A unity gain, differential amplifier is provided for remote voltage
sensing and completely eliminates any potential difference
between remote and local grounds. This improves regulation
and protection accuracy. The threshold-sensitive enable input is
available to accurately coordinate the start-up of the
ISL6334AR5368 with any other voltage rail. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting.
®
1
Data Sheet
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Intel VR11.1 Compliant
• Proprietary Active Pulse Positioning (APP) and Adaptive
• Proprietary Active Phase Adding and Dropping with Diode
• Precision Multiphase Core Voltage Regulation
• Precision resistor or DCR Differential Current Sensing
• Microprocessor Voltage Identification Input
• Average Overcurrent Protection and Channel Current Limit
• Precision Overcurrent Protection on IMON Pin
• Thermal Monitoring and Overvoltage Protection
• Integrated Programmable Temperature Compensation
• Integrated Open Sense Line Protection
• 1- to 4-Phase Operation, Coupled Inductor Compatibility
• Adjustable Switching Frequency up to 1MHz Per Phase
• Package Option
• Pb-Free (RoHS Compliant)
Phase Alignment (APA) Modulation Scheme
Emulation Scheme For High Light Load Efficiency
- Differential Remote Voltage Sensing
- ±0.5% Closed-loop System Accuracy Over Load, Line
- Bi-directional, Adjustable Reference-Voltage Offset
- Accurate Load-Line (Droop) Programming
- Accurate Channel-Current Balancing
- Accurate Load Current Monitoring via IMON Pin
- Dynamic VID™ Technology for VR11.1 Requirement
- 8-Bit VID, VR11 Compatible
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
September 7, 2010
and Temperature
Flat No Leads - Product Outline
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
ISL6334AR5368
FN6839.2

Related parts for ISL6334ACRZR5368

ISL6334ACRZR5368 Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6334AR5368 ...

Page 2

... Ordering Information PART NUMBER (Notes 2, 3) ISL6334AIRZR5368 6334A IRZ ISL6334AIRZ-TR5368 (Note 1) 6334A IRZ ISL6334ACRZR5368 6334A CRZ ISL6334ACRZ-TR5368 (Note 1) 6334A CRZ NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 3

... Dual ISL6614, ISL6614A 12V Quad ISL6610, ISL6610A 5V Quad NOTE: Note: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels. 3 ISL6334AR5368 COMMENTS GATE DIODE DRIVE ...

Page 4

ISL6334AR5368 Block Diagram VDIFF - RGND X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFS OFFSET REF FB COMP 1.11V + OCP - IMON 1.11V ...

Page 5

Typical Application: 4-Phase VR with Integrated Thermal Compensation, PSI# (DE and GVOT) +5V COMP VCC DAC FB REF VDIFF VSEN PWM1 RGND ISEN1- EN_VTT VTT ISEN1+ VR_RDY VID7 ISL6334 ISL6334AR5368 VID6 VID5 VID4 PWM2 VID3 VID2 ISEN2- VID1 ISEN2+ VID0 ...

Page 6

Typical Application - 4-Phase VR with 1-Phase PSI# and without Diode Emulation and GVOT +5V COMP VCC FB VDIFF VSEN PWM1 RGND ISEN1- EN_VTT VTT ISEN1+ VR_RDY VID7 ISL6334 ISL6334AR5368 VID6 VID5 VID4 PWM2 VID3 VID2 ISEN2- VID1 ISEN2+ VID0 ...

Page 7

Typical Application -VR with External Thermal Compensation, 2-Phase PSI# (no DE and GVOT) NTC + COMP VCC FB VDIFF VSEN RGND ISEN1+ EN_VTT VTT ISEN1- VR_RDY PWM1 VID7 VID6 ISL6334 ISL6334AR5368 VID5 VID4 VID3 PWM3 VID2 ISEN3- VID1 ...

Page 8

... Ld 6x6 QFN Package . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp TEST CONDITIONS VCC = 5VDC; EN_PWR = 5VDC 100kΩ, T ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA VCC = 5VDC; EN_PWR = 0VDC 100kΩ ...

Page 9

Electrical Specifications Operating Conditions: VCC = 5V Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS Pin OSCILLATORS Accuracy of Switching Frequency Setting Adjustment ...

Page 10

Electrical Specifications Operating Conditions: VCC = 5V Unless Otherwise Specified. Boldface limits apply over the operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued) PARAMETER TM Input Voltage for VR_FAN Reset TM Input Voltage for VR_HOT Trip TM ...

Page 11

... PWM1, PWM2, PWM3, PWM4 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM2, PWM3 and PWM4. Tie PWM2 to VCC to configure for 1-phase operation. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...

Page 12

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have ...

Page 13

... Figure 21 shows the single phase input-capacitor RMS current for comparison. PWM Modulation Scheme The ISL6334AR5368 adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads ...

Page 14

... PWM potential, but not lower it below the 14 ISL6334AR5368 level set by the controller IC. Therefore, the controller’s PWM outputs are directly compatible with Intersil drivers that require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal amplitudes are generally incompatible. Switching Frequency ...

Page 15

... The resulting average current I total load current. Channel current balance is achieved by ) close to 27ns. T comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method. DCR ⋅ I ----------------- - = ...

Page 16

... The output of the error amplifier, V COMP sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry, which control voltage regulation, are illustrated in Figure 6. ...

Page 17

TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...

Page 18

TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...

Page 19

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes. The magnitude of the spike is dictated ...

Page 20

... It is important that the driver reach their POR level before the ISL6334AR5368 becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6334AR5368 with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR ...

Page 21

... This causes IMON is the total the Intersil drivers to turn on the lower MOSFETs and pull LOAD is the sense resistor the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM signals enter a high-impedance state ...

Page 22

... IMON to GND. At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns, commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft-start ...

Page 23

There are two comparators with hysteresis to compare the TM pin voltage to the fixed thresholds for VR_FAN and VR_HOT signals respectively. The VR_FAN signal is set to high when the TM voltage is lower than 39.1% of VCC voltage, ...

Page 24

TM1 NON-LINEAR TM A NTC TC1 4-BIT TCOMP DROOP AND A/D OVERCURRENT PROTECTION R TC2 FIGURE 15. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE COMPENSATION When the TM ...

Page 25

... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs, which include schematics, bills of materials, and example board layouts for all common microprocessor applications ...

Page 26

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time Equation 27, the 2 approximate power loss UP,2 ⎛ ⎞ t ⎛ ⎞ ≈ M P-P ...

Page 27

Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING LOAD-LINE ...

Page 28

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing ...

Page 29

... Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals ...

Page 30

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 31

Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 31 ...

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