EVB-LAN7500-LC SMSC, EVB-LAN7500-LC Datasheet - Page 49

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EVB-LAN7500-LC

Manufacturer Part Number
EVB-LAN7500-LC
Description
EVALUATION BOARD FOR LAN7500
Manufacturer
SMSC
Datasheets

Specifications of EVB-LAN7500-LC

Design Resources
EVB-LAN7500-LC BOM EVB-LAN7500-LC Gerber Files EVB-LAN7500-LC Schematic
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN7500
Primary Attributes
USB 2.0 to 10/100/1000 Ethernet Controller
Secondary Attributes
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1105
EVB-LAN7500
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
SMSC LAN7500/LAN7500i
7.5.3
Power Supplies
SYMBOL
t
t
purstd
purstv
t
All External
rstia
nRESET
Power-On Reset Timing
Figure 7.3
(nRESET assertion) is required following power-on. For proper operation, nRESET must be asserted
for no less than t
t
Note: nRESET deassertion must be monotonic.
purstd
External power supplies at operational level to nRESET
deassertion
External power supplies at at operational level to
nRESET valid
nRESET input assertion time
after all external power supplies have reached operational levels.
illustrates the nRESET timing requirements in relation to power-on. A hardware reset
V
opp
rstia
. The nRESET pin can be asserted at any time, but must not be deasserted before
Table 7.16 nRESET Power-On Timing Values
DESCRIPTION
Figure 7.3 nRESET Power-On Timing
t
purstv
DATASHEET
t
49
purstd
t
rstia
MIN
100
25
0
TYP
Revision 1.0 (11-01-10)
MAX
UNITS
mS
nS
μS

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