EVB-LAN7500-LC SMSC, EVB-LAN7500-LC Datasheet - Page 50

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EVB-LAN7500-LC

Manufacturer Part Number
EVB-LAN7500-LC
Description
EVALUATION BOARD FOR LAN7500
Manufacturer
SMSC
Datasheets

Specifications of EVB-LAN7500-LC

Design Resources
EVB-LAN7500-LC BOM EVB-LAN7500-LC Gerber Files EVB-LAN7500-LC Schematic
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN7500
Primary Attributes
USB 2.0 to 10/100/1000 Ethernet Controller
Secondary Attributes
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1105
EVB-LAN7500
Revision 1.0 (11-01-10)
7.5.4
nRESET
SYMBOL
t
rstia
Reset Timing
Figure 7.3
no less than t
Note: A hardware reset (nRESET assertion) is required following power-on. Refer to
nRESET input assertion time
"Power-On Reset Timing," on page 49
illustrates the nRESET pin timing requirements. When used, nRESET must be asserted for
rstia
.
DESCRIPTION
t
rstia
Table 7.17 nRESET Timing Values
Figure 7.4 nRESET Timing
DATASHEET
50
for additional information.
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
MIN
1
TYP
SMSC LAN7500/LAN7500i
MAX
Section 7.5.3,
Datasheet
UNITS
μS

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