NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet
NAU8812EVB
Specifications of NAU8812EVB
Related parts for NAU8812EVB
NAU8812EVB Summary of contents
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GENERAL DESCRIPTION The NAU8812 is a cost effective and low power wideband MONO audio CODEC designed for voice telephony related applications. Functions include Automatic Level Control (ALC) with noise gate, PGA, standard audio interface ...
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PIN CONFIGURATION VREF MIC - MIC + MICBIAS NC VDDA VSSA VSSA VDDC VDDB VSSD ADCOUT DACIN VDDA 2 VSSA 3 VSSA 4 5 VDDL VDDC 6 VDDB 7 VSSD 8 emPowerAudio ™ Datasheet Revision 2.0 ...
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PIN DESCRIPTION Pin Name 28-Pin 32-Pin VREF 1 29 Decoupling internal analog mid supply reference MIC Microphone Negative Input voltage MIC Microphone Positive Input MICBIAS 4 32 Microphone Bias Connect VDDA ...
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BLOCK DIAGRAM Figure 3: NAU8812 General Block Diagram emPowerAudio ™ Datasheet Revision 2.0 Page 4 of 109 NAU8812 DACIN BCLK FS ADCOUT SO SCLK SDIO MODE CSb/GPIO MCLK January 2011 ...
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Table of Contents 6. 1. GENERAL DESCRIPTION .................................................................................................................................. 1 2. FEATURES ......................................................................................................................................................... 1 3. PIN CONFIGURATION ....................................................................................................................................... 2 4. PIN DESCRIPTION ............................................................................................................................................. 3 5. BLOCK DIAGRAM .............................................................................................................................................. 4 6. TABLE OF CONTENTS ...................................................................................................................................... 5 7. LIST OF FIGURES .............................................................................................................................................. 9 ...
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Jack Detect ......................................................................................................................................... 40 12.7.3. Thermal Shutdown .............................................................................................................................. 41 12.8. CLOCK GENERATION BLOCK ................................................................................................................. 42 12.9. CONTROL INTERFACE ............................................................................................................................ 46 12.9.1. SPI Serial Control ................................................................................................................................ 46 12.9.1.1. 16-bit Write Operation (default) ................................................................................................... 47 12.9.1.2. 24-bit Write Operation ................................................................................................................. 47 ...
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ALC1 REGISTER ................................................................................................................................ 74 13.6.2. ALC2 REGISTER ................................................................................................................................ 75 13.6.3. ALC3 REGISTER ................................................................................................................................ 76 13.7. NOISE GAIN CONTROL REGISTER......................................................................................................... 77 13.8. PHASE LOCK LOOP (PLL) REGISTERS .................................................................................................. 78 13.8.1. PLL Control Registers ......................................................................................................................... 78 13.8.2. Phase Lock Loop Control ...
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ENCODE DECODE CHARACTERISTICS ..................................................................................... 98 15.9. A-LAW ENCODE DECODE CHARACTERISTICS..................................................................................... 99 15.10. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE ........................................................................ 100 15.11. µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW) .................................................................................. 100 16. DIGITAL FILTER CHARACTERISTICS .......................................................................................................... ...
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List of Figures 7. Figure 1: 28-Pin SSOP Package ................................................................................................................................... 2 Figure 2: 32-Pin QFN Package ..................................................................................................................................... 2 Figure 3: NAU8812 General Block Diagram ................................................................................................................. 4 Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[ .............................................................................. 17 Figure ...
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Figure 37: PCM Mode Audio Interface (Normal Mode) ............................................................................................... 55 Figure 38: PCM Mode Audio Interface (Special mode) ............................................................................................... 55 Figure 39: PCM Time Slot Mode (Time slot = 0) (Normal Mode) ................................................................................ 56 Figure 40: PCM Time Slot Mode ...
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List of Tables Table 1: Pin Description for SSOP and QFN Packages ................................................................................................ 3 Table 2: Register associated with Input PGA Contro .................................................................................................. 18 Table 3: Microphone Non-Inverting Input Impedances ................................................................................................. 19 Table 4: Microphone Inverting Input Impedances ....................................................................................................... ...
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ABSOLUTE MAXIMUM RATINGS CONDITION VDDB, VDDC, VDDA supply voltages VDDSPK supply voltage (MOUT=0, SPKBST=0) VDDSPK supply voltage (MOUTBST=1, SPKBST=1) Core Digital Input Voltage range Buffer Digital Input Voltage range Analog Input Voltage range Industrial operating temperature Storage temperature range ...
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ELECTRICAL CHARACTERISTICS VDDC = 1.8V, VDDA = VDDB = SPKBST = 3.3V, T otherwise stated. PARAMETER SYMBOL Analogue to Digital Converter (ADC) 1 Full scale input signal V INFS 2 Signal to Noise Ratio SNR 3 Total Harmonic Distortion ...
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VDDC = 1.8V, VDDA = VDDB = SPKBST = 3.3V, T otherwise stated. PARAMETER SYMBOL BTL Speaker Output (SPKOUT+, SPKOUT- with 8Ω bridge tied load) 7 Full scale output Output Power PO Signal to Noise Ratio SNR Total Harmonic Distortion ...
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VDDC = 1.8V, VDDA = VDDB = SPKBST = 3.3V, T otherwise stated. PARAMETER SYMBOL Automatic Level Control (ALC)/Limiter – ADC only 5, 6 Gain Ramp-Up (Decay) Time t DCY Gain Ramp-Down (Attack) Time ATK Digital Input ...
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FUNCTIONAL DESCRIPTION The NAU8812 is a MONO Audio CODEC with very robust ADC and DAC. The device provides one single ended auxiliary input (AUX pin) and one differential microphone input (MIC- & MIC+ pins). The auxiliary input (AUX) can ...
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The last two paths above go through the ADC filters where the ALC loop controls the amplitude of the input signal. The device also has an internal configurable biasing circuit for biasing the microphone, reducing external components. An internal inverting ...
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The differential microphone input (MIC- & MIC+ pins) The NAU8812 features a low-noise, high common mode rejection ratio (CMRR), differential microphone inputs (MIC- & MIC+ pins) which are connected to a PGA Gain stage. The differential input structure is ...
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Positive Microphone Input (MIC+) The positive microphone input (MIC+) can be used as part of the differential input. It connects to the positive terminal of the PGA gain amplifier by setting PMICPGA[0] address (0x2C) to HIGH or can be ...
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When the associated control bit is set logic = 1, the MIC- pin is connected to a resistor of approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click ...
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The signal from AUX stage can be amplified at the PGA Boost stage before connecting to the Boost Mixer by setting a binary value from “001” - “111” to AUXBSTGAIN[2:0] address (0x2F). The path is disconnected by setting “000” to ...
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MICROPHONE BIASING VREF Figure 8: Microphone Bias Schematic The MICBIAS pin is a low-noise microphone bias source for an external microphone, which can provide a maximum of 3mA of bias current. This DC bias voltage is suitable for powering ...
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MICBIASV[8: Table 8: Microphone Bias Voltage Control emPowerAudio ™ Datasheet Revision 2.0 Microphone Bias Voltage Control MICBIASM[ MICBIASM[4 0.9* VDDA 0.85* VDDA 1 0.65* VDDA 0.60* VDDA 0 0.75* VDDA 0.70* VDDA ...
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ADC DIGITAL FILTER BLOCK Digital Digital ADC Decimator Filter Figure 9: ADC Digital Filter Path Block Diagram The ADC digital filter block performs a 24-bit signal processing. The block consists of an oversampled analog sigma- delta modulator, digital decimator, ...
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Programmable High Pass Filter (HPF) The high pass filter (HPF) has two different modes that it can operate in either Audio or Application mode HPFAM[7] address (0x0E). In Audio Mode (HPFAM=0) the filter is first order, with a cut-off ...
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A 0 b tan 1 s Coefficient 1 b tan 1 ...
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Input PGA Pin The ALC is enabled by setting ALCEN[8] address (0x20) bit to HIGH. The ALC has two functional modes, which is set by ALCM[8] address (0x22). Normal mode (ALCM = LOW) Peak Limiter mode (ALCM = ...
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Inhibition of gain increment during noise inputs Limiter mode operation Bit(s) Addr ALCMNGAIN[2:0] Minimum Gain of PGA ALCMXGAIN[2:0] Maximum Gain of PGA 0x20 ALCEN[8] Enable ALC function ALCSL[3:0] ALC Target ALCHT[3:0] ALC Hold Time 0x21 ALCZC[8] ALC Zero ...
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Normal Mode Normal mode is selected when ALCM[8] address (0x22) is set LOW and the ALC is enabled by setting ALCEN[8] address (0x20) HIGH. This block adjusts the PGA gain setting up and down in response to the input ...
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PGA Input PGA Output PGA Gain Hold Delay Change 12.4.2. Peak Limiter Mode Peak Limiter mode is selected when ALCM[8] address (0x22) is set to HIGH and the ALC is enabled by setting ALCEN[8] address (0x20). In limiter mode, the ...
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Attack Time When the absolute value of the ADC output exceeds the level set by the ALC threshold, ALCSL[3:0] address (0x21), attack mode is initiated at a rate controlled by the attack rate register ALCATK[3:0] address (0x22). The peak ...
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PGA Input PGA Output PGA Gain Figure 16: ALC Operation with Noise Gate Enabled 12.4.6. Zero Crossing The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register setting when the ALC ...
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DAC DIGITAL FILTER BLOCK DAC Digital Filters Digital Digital Audio Gain Interface The DAC digital block uses 24-bit signal processing to generate analog audio with a 16-bit digital sample stream input. This block consists of a sigma-delta modulator, high ...
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DAC Soft Mute The NAU8812 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is disabled ...
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The DAC output can be inverted (phase inversion) by setting DACPL[1:0] address (0x0A) to HIGH, non-inverted output is set by ...
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ANALOG OUTPUTS The NAU8812 features two different types of outputs, a single-ended MONO output (MOUT) and a differential speaker outputs (SPKOUT+ and SPKOUT-). configuration referred to as Bridge-Tied Load (BTL). Output from DACOUT[0] Auxiliary Amplifier (0x38) DAC Output SIDETONE ...
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Bit(s) Addr SPKMXEN[2] 0x03 Speaker Mixer enable Speaker positive terminal PSPKEN[5] 0x03 enable Speaker negative terminal NSPKEN[6] 0x03 enable SPKATT[1] 0x28 Speaker output attenuation SPKBST[2] 0x31 Speaker output Boost SPKGAIN[5:0] 0x36 Speaker output Volume SPKMT[6] 0x36 Speaker output Mute 12.6.2. ...
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Unused Analog I/O AUX 30k AUXEN[6] (0x01) MIC- 30k NMICPGA[1] (0x2C) MIC+ 40k PMICPGA[0] (0x2C) 1.0 x VREF VREF SBUFL[6] IOBUFEN[2] (0x4F) (0x01) SBUFH[7] DCBUFEN[8] (0x4F) (0x01) 1.5 x VREF R R Figure 20: Tie-off Options for the Speaker ...
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The goal to reduce pops and clicks is to insure that the charge voltage on these capacitors does not change suddenly at any time. When an input or output not-used operating condition, it ...
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Addr 0x08 0x07 12.7.1. Slow Timer Clock An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively long period of time, or time-spans. This enables ...
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Bit(s) Addr GPIOSEL[2:0] 0x08 GPIO select GPIOPL[3] 0x08 GPIO polarity GPIOPLL[4:5] 0x08 GPIO PLL divider PSPKEN[5] 0x03 Speaker positive terminal enable NSPKEN[6] 0x03 Speaker negative terminal enable MOUTEN[7] 0x03 MONO Output enable SCLKEN[0] 0x07 Slow clock enable Table 21: Jack ...
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CLOCK GENERATION BLOCK PLLMCLK[4] (0x24) f MCLK PLL1 1 R=f 2 f/2 PLL BLOCK … GPIO1 /CSb GPIO1SEL[2:0] (0x08) Figure 21: PLL and Clock Select Circuit The NAU8812 has two basic clock modes that support the ADC and DAC ...
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Addr 0x01 DCBUFEN 0 AUXEN 0x06 CLKM MCLKSEL[2:0] 0x07 0x24 0x25 0x26 0x27 Table 23: Registers associated with PLL In Master Mode, the IMCLK signal is used to ...
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In summary, for any given design, choose: Equations IMCLK = (256) * (desired codec IMCLK = desired Master Clock sample rate) where P is the Master Clock divider IMCLK) integer value; 2 optimal f ...
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To complete this portion of the design example, the integer portion of the multiplier is truncated to the value, 8 and the fractional portion is multiplied this is: (2 )(0.192) = 3221225.472 best to round ...
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CONTROL INTERFACE The NAU8812 features two serial bus interfaces SPI and 2-Wire that provide access to the control registers. The MODE pin in conjunction with SPIEN[8] (address 0x49) as shown in the following Table selects the control interfaces. 2-Wire ...
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Write Operation (default) The default control interface architecture is SPI 16-bit. This interface architecture consists of 7-bits of control register address, and 9-bits of control register data. The MODE Pin set to “1” (HIGH) selects the SPI 16-bit. ...
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CBb/GPIO SCLK SDIO Device Address = 10h Figure 23: Register Write operation using a 24-bit SPI Interface 12.9.1.3. 32-bit Read Operation The 32-bit read operation is a four-byte operation with 2-bytes of data. The transmission starts ...
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Protocol Convention All 2-Wire interface operations must begin with a START condition, which is a HIGH to LOW transition of SDIO while SCLK is HIGH. All 2-Wire and all interface operations are terminated by a STOP condition, which ...
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SCLK SDIO Device Address = 34h T 12.9.2.3. 2-WIRE Read Operation A Read operation consists of a three-byte instruction followed by one or more Data Bytes. The master ...
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DIGITAL AUDIO INTERFACES NAU8812 only uses the Left channel to transfer data in normal mode. It supports an independent digital interface for voice and audio. The digital interface is used to input digital data to the DAC, or output ...
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Right Justified audio data In right justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel data is transferred during the HIGH frame sync. The MSB data is sampled first. The ...
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Left Justified audio data In Left justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel data is transferred during the HIGH frame sync. The MSB data is sampled first and ...
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I S audio data interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel data is transferred during the LOW frame sync. The MSB data is sampled ...
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PCM audio data In PCM interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel data is transferred during the LOW frame sync. The MSB data is sampled first. The data is ...
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PCM Time Slot audio data In PCM Time-Slot interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel data is transferred during the LOW frame sync. The MSB data is sampled first. ...
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Companding Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit rates, and make use of non-linear algorithms. NAU8812 supports two different types of companding A-law and µ-law on both transmit and receive sides. ...
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POWER SUPPLY This device has been designed to operate reliably using a wide range of power supply conditions and power- on/power-off sequences. There are no special requirements for the sequence or rate at which the various power supply pins ...
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Although it is not required strongly recommended that a Software Reset command should be issued after power- on and after the power-on-reset condition is ended. This will help insure reliable operation under every power sequencing condition that could ...
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Name VDDSPK - 3.3V operation MOUTMXEN[3] MOUTEN[7] Output stages NSPKEN[6] PSPKEN[5] Un-mute DAC DACMT[ Name Un-mute DAC Power Management Output stages Power supplies 12.11.5. Reference Impedance (REFIMP) and Analog Bias Before the device is functional or any of ...
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To each lowest power possible after the device is functioning set ABIASEN[3] address (0x01) bit to LOW. Addr 0x01 DCBUFEN 0 AUXEN 0x0A 0 0 DACMT 0x0E MOUTFEN MOUTFAM ...
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REGISTER DESCRIPTION Register Address Register Names DEC HEX Software Reset 1 01 Power Management 1 DCBUFEN 2 02 Power Management Power Management 3 0 MOUTEN 4 04 Audio Interface BCLKP FSP 5 ...
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Register Address Register Names DEC HEX PGA Gain 0 PGAZC 47 2F ADC Boost PGABST 49 31 Output CTRL Mixer CTRL SPKOUT Volume 0 SPKZC 56 38 MONO Mixer Control 0 ...
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SOFTWARE RESET Addr 0x00 This is device Reset register. Performing a write instruction to this register with any data will reset all the bits in the register map to default. 13.2. POWER MANAGEMENT REGISTERS 13.2.1. Power ...
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Power Management 2 Addr 0x02 Name Bit 0 1 13.2.3. Power Management 3 Addr 0x03 0 MOUTEN NSPKEN PSPKEN MOUT SPKOUT- Name Enable Enable Bit MOUTEN[7] NSPKEN[6] 0 Disable Disable ...
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Word Length Selection WLEN[6] WLEN[5] Bits 13.3.2. Audio Interface Companding Control Addr 0x05 The NAU8812 provides a Digital Loopback ADDAP[0] address (0x05) ...
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Clock Control Register Addr 0x06 CLKM MCLKSEL[2:0] Master Clock Selection MCLKSEL MCLKSEL MCLKSEL [7] [6] [ ...
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Audio Sample Rate Control Register Addr 0x07 The Audio sample rate configures the coefficients for the internal digital filters SMPLR[ NAU8812 provides a slow clock ...
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GPIO Control Register Addr 0x08 GPIOSEL [ PLL Output Clock Divider GPIOPLL[5] GPIOPLL[ 13.3.6. DAC Control Register Addr ...
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DEEMP[ 13.3.7. DAC Gain Control Register Addr 0x0B DAC Gain Range -127dB to 0dB @ 0.5 increments ...
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High Pass Filter HPF[6] HPF[5] HPF[ 13.3.9. ADC Gain Control Register Addr D8 ...
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DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS Addr D8 D7 0x18 DACLIMEN DACLIMDCY[3:0] 0x19 0 0 DAC Limiter Decay time (per 6dB gain change) for 44.1 kHz sampling. Note that these will scale with sample rate DACLIMDCY[3: ...
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DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) DACLIMTHL[3: ...
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Name A 0 tan s Coefficient tan ...
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ALC2 REGISTER Addr 0x21 ALCZC ALCHT[3:0] ALC HOLD TIME before gain is increased. ALCHT[3: Time Doubles with every increment 1 ...
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ALC3 REGISTER Addr 0x22 ALCM ALCDCY[3:0] ALCDCY[3: Per Step 500 Time doubles with every increment ...
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NOISE GAIN CONTROL REGISTER Addr 0x23 Noise Gate Enable Bit ALCNEN[3] 0 Disabled 1 Enabled emPowerAudio ™ Datasheet Revision 2 ALCNEN ALCNTH[2:0] Noise Gate Threshold ALCNTH[2:0] Mode ...
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PHASE LOCK LOOP (PLL) REGISTERS 13.8.1. PLL Control Registers Addr 0x24 PLL Integer PLLN[3: ...
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INPUT, OUTPUT, AND MIXERS CONTROL REGISTER 13.9.1. Attenuation Control Register Addr 0x28 Attenuation control for bypass path (output of Name input boost stage) to speaker mixer and MONO Bit 0 1 13.9.2. Input ...
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PGA Gain Control Register Addr 0x2D 0 PGAZC PGAMT ::: ::: PGA Gain Range -12dB to +35.25dB @ 0.75 ::: ::: PGA Zero Cross Enable ...
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ADC Boost Control Registers Addr 0x2F PGABST 0 MIC+ pin to the input Boost Stage (NB, when using this path set PMICPGA=0): PMICBSTGAIN[2: Disconnected ...
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Speaker Mixer Control Register Addr 0x32 Auxiliary to Speaker Mixer Bit AUXSPK[5] 0 Disconnected 1 Connected 13.9.7. Speaker Gain Control Register Addr 0x36 0 SPKZC SPKMT ...
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MONO Mixer Control Register Addr 0x38 0 0 MOUTMXMT MOUT Mute Bit MOUTMXMT[6] 0 Not Muted 1 Muted During mute, the MONO output will output VREF that can be used reference for a ...
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PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL 13.10.1. PCM1 TIMESLOT CONTROL REGISTER Addr 0x3B Transmit and receive timeslot are expressed in number of BCLK cycles in a 10-bit word. The most significant bit TSLOT[9] ...
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Internal ADC Power Up and Down out data Output Enable iADCOUT PUDOEN[ 13.11. REGISTER ID (READ ONLY) 13.11.1. Device revision register Addr 0x3E READ ...
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Reserved Addr 0x41 13.13. OUTPUT Driver Control Register Addr 0x45 0 Bit Bit Description Bit Name Location Override to automatic HVOP 0 3V/5V bias selection Update bit for HV 2 ...
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AUTOMATIC LEVEL CONTROL ENHANCED REGISTER 13.14.1. ALC1 Enhanced Register Addr 0x46 0 ALCPKSEL ALCNGSEL Bit Bit Description Location 5:0 Display PGA and ALC Gain Choose peak or peak-to-peak value 6 for Noise Gate threshold logic Choose ...
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MISC CONTROL REGISTER Addr 0x49 SPIEN FSERRVAL[1:0] FSERFLSH FSERRENA NFDLY DACINMT PLLLOCKP DACOS256 0x000 Bit Bit Description Location Set DAC to use 256x 0 oversampling rate Enable control to use PLL 1 output when PLL is ...
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Output Tie-Off REGISTER Addr 0x4B 0 LPSPKA Bit Bit Description Location Direct manual control for switch for 0 VREF 6k-ohm resistor to ground Direct manual control for switch for 1 VREF 160k-ohm resistor to ground Direct ...
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AUTOMUTE CONTROL AND STATUS READ REGISTER Addr 0x4E 0 0 AMTCTRL HVDET NSGATE Bit Bit Description Location 0 Peak limiter indicator READ ONLY BIT 2 Digital Mute function of the DAC READ ONLY BIT 3 Analog ...
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CONTROL INTERFACE TIMING DIAGRAM 14.1. SPI WRITE TIMING DIAGRAM CSB T SCK SCLK T SCKH T SDIO T SDIOS Figure 42: SPI Write Timing Diagram 14.2. SPI READ TIMING DIAGRAM CSB T CSSCS T SCK SCLK T SCKH SDIO ...
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SYMBOL DESCRIPTION T SCLK Cycle Time SCK T SCLK High Pulse Width SCKH T SCLK Low Pulse Width SCKL T Rise Time for all SPI Signals RISE T Fall Time for all SPI Signals FALL st CSb Falling Edge to ...
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TIMING DIAGRAM T T STAH SDIOS SCLK T SCKH SDIO T T SCKL SYMBOL DESCRIPTION START / Repeat START condition, SCLK falling edge to T STAH SDIO falling edge hold timing Repeat START condition, SDIO rising edge to ...
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AUDIO INTERFACE TIMING DIAGRAM 15.1. AUDIO INTERFACE IN SLAVE MODE BCLK (Slave) T FSH T FSS FS (Slave) DACIN T DOD ADCOUT Figure 45: Audio Interface Slave Mode Timing Diagram 15.2. AUDIO INTERFACE IN MASTER MODE BCLK (Master) T ...
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PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data) BCLK (Slave FSH FSH T T FSS FS (Slave) DACIN T DOD ADCOUT Figure 47: PCM Audio Interface Slave Mode Timing Diagram 15.4. PCM AUDIO INTERFACE IN MASTER ...
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PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode ) BCLK (Slave FSH FSH T T FSS FSS FS (Slave) DACIN MSB T DOD1 T DOD ADCOUT MSB Figure 49: PCM Audio Interface Slave Mode (PCM ...
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SYMBOL DESCRIPTION T BSCK Cycle Time (Slave Mode) BCK T BSCK High Pulse Width (Slave Mode) BCKH T BSCK Low Pulse Width (Slave Mode) BCKL SCK Rising Edge Setup Time (Slave Mode) FSS T SCK Rising Edge ...
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ENCODE DECODE CHARACTERISTICS Normalized Encode Decision Sign Chord Chord Levels 8159 7903 : : : : 4319 4063 : : : : 2143 2015 : : ...
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A-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode D7 D6 Decision Sign Chord Chord Levels 4096 1 0 3968 : : : 2176 1 0 2048 : : : 1088 1 0 1024 : : : 544 1 0 512 : ...
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A-LAW CODES FOR ZERO AND FULL SCALE µ-Law Level Sign bit Chord bits (D7) (D6,D5,D4) + Full Scale 1 000 + Zero 1 111 - Zero 0 111 - Full Scale 0 000 15.11. µ-LAW / A-LAW ...
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DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 57 Digital Filter Characteristics TERMINOLOGY ...
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Figure 52: DAC Filter Frequency Response Figure 54: DAC Filter Ripple emPowerAudio ™ Datasheet Revision 2.0 Figure 53: ADC Filter Frequency Response Figure 55: ADC Filter Ripple Page 102 of 109 NAU8812 January 2011 ...
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TYPICAL APPLICATION C9 4.7uF VREF C8 1uF MIC - C7 1uF MIC + R1 R2 1.2k ohm 1.2k ohm MICBIAS C6 NC 4.7uF VDDA VDDA VSSA VSSA VDDC VDDC VDDB VDDB 4.7uF 4.7uF 4.7uF VSSD VSS ...
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C8 1uF C7 1uF R2 R1 1.2k ohm 1.2k ohm MICBIAS C6 4.7uF NC VDDA VDDA VSSA VSSA C11 10nF VDDL VDDC VDDC VDDB VDDB VSSD 4.7uF 4.7uF 4.7uF VSS Figure 57: Application Diagram for 32-Pin QFN ...
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PACKAGE SPECIFICATION 18.1. 28 Pin SSOP SEATING PLANE DIMENS SYMBOL MIN. A 0.05 A1 1.65 1.75 A2 0.22 b 0.09 c 10.20 10.05 D 5.00 5.30 E ...
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QFN emPowerAudio ™ Datasheet Revision 2.0 Page 106 of 109 NAU8812 January 2011 ...
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ORDERING INFORMATION Nuvoton Part Number Description NAU8812_ _ Package Material Package Type emPowerAudio ™ Datasheet Revision 2.0 Pb-free Package 28-Pin SSOP Package 32-Pin QFN Package Page 107 of 109 NAU8812 January 2011 ...
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VERSION HISTORY VERSION DATE PAGE 1.0 September 2009 1.1 November 2009 108 1.2 December 2009 1.3 January 2010 107 1.4 January 2010 1.5 February 2010 63, 87 1.6 March 2010 ...
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Nuvoton customers using or selling these products for use in such applications their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. emPowerAudio ™ Datasheet Revision 2.0 Page ...