ISL6421AEVAL1Z Intersil, ISL6421AEVAL1Z Datasheet

ISL6421AEVAL1Z

Manufacturer Part Number

ISL6421AEVAL1Z

Description

EVAL BOARD 1 FOR ISL6421A

Manufacturer

Intersil

Datasheet

1.ISL6421AERZ.pdf (12 pages)

Specifications of ISL6421AEVAL1Z

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Current page: 1 of 12
Download datasheet (411Kb)

Single Output LNB Supply and Control

Voltage Regulator with I

Advanced Satellite Set-top Box Designs

The ISL6421A is a highly integrated solution for providing

power and control signals from advanced satellite set-top

box (STB) modules to the low noise block (LNB). The

internal architecture of this device contains a current-mode

boost PWM and a low-noise linear regulator, along with the

circuitry required for I

DiSEqC™ standard control signals to the LNB.

A regulated output voltage is available at the output terminal

(VOUT) to support the operation of the antenna port in

advanced satellite STB applications. The regulated output

may be set to either 13V or 18V by use of the voltage select

command bit (VSEL) through the I

compensate for the voltage drop in the coaxial cable, the

voltage may be increased by 1V with the line length

compensation bit (LLC) feature. The device can be put into a

standby mode by means of the enable bit (EN), this disables

the PWM and Linear regulator combination and helps

conserve power.

The input to the linear regulator is derived from the current

mode boost converter, such that the required voltage is the

sum of the output voltage and the linear regulator drop (1.0V

typical). This ensures that the power dissipation is minimized

and maintains a constant voltage drop across the linear pass

element, while permitting an adequate voltage range for tone

injection.

The device is capable of providing 450mA (typical). The

overcurrent limit is either digitally or resistor programmable.

Pinout

BYPASS

SEL18V

PGND

SGND

PGND

GATE

ISL6421A (QFN) TOP VIEW

C device interfacing and for providing

C bus. Additionally, to

C Interface for

Data Sheet

CPSWOUT

AGND

VOUT

DSQIN

TCAP

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• Switch-Mode Power Converter for Lowest Dissipation

• I

• Built-In Tone Oscillator Factory Trimmed to 22kHz

• Internal Over Temperature Protection and Diagnostics

• Internal Overload and Over Temperature Flags

• Output Back-Bias Protection to 24V

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

• External Pins to Select 13V/18V Options

• Pb-Free Available (RoHS Compliant)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and

Ordering Information

*Add -T for tape and reel package.

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6421AER

ISL6421AERZ

(Note)

- Boost PWM with >92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

- Vsw tracks Vout ensures low dissipation

- Registered Slave Address 0001 00XX

- Fully Functional 3.3V, 5V Operation up to 400kHz

- Facilitates DiSEqC™ (EUTELSAT) Encoding

- External Modulation input DSQIN

(Visible on I

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

- Near Chip-Scale Package Footprint

Surface Mount Guidelines for QFN Packages”; Available

on the Intersil website, www.intersil.com

NUMBER*

C Compatible Interface for Remote Device Control

PART

No Leads - Product Outline

All other trademarks mentioned are the property of their respective owners.

March 9, 2006

Intersil (and design) is a registered trademark of Intersil Americas Inc.

ISL6421AER

ISL6421AERZ -20 to 85 32 Ld 5x5 QFN

MARKING

PART

-20 to 85 32 Ld 5x5 QFN L32.5x5

RANGE

TEMP.

(°C)

(Pb-free)

PACKAGE

ISL6421A

FN9167.3

L32.5x5

DWG. #

PKG.

Related parts for ISL6421AEVAL1Z

ISL6421AEVAL1Z Summary of contents

Page 1

... All other trademarks mentioned are the property of their respective owners. ISL6421A FN9167 TEMP. PART RANGE MARKING (°C) PACKAGE ISL6421AER - 5x5 QFN L32.5x5 ISL6421AERZ - 5x5 QFN (Pb-free) | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved PKG. DWG. # L32.5x5 ...

Page 2

Block Diagram OVERCURRENT COUNTER PROTECTION LOGIC SCHEME 1 PWM LOGIC GATE Q PGND ILIM CS AMP CS COMPENSATION COMP FB VSW VOUT ON CHIP VCC LINEAR UVLO SGND POR SOFT-START INT 5V SOFT-START EN SEL18V OLF DCL OC CLK S ...

Page 3

Typical Application Schematic NOTE: SGND and PGND to be shorted as close layout ...

Page 4

Absolute Maximum Ratings Supply Voltage 8.0V to 18.0V CC Logic Input Voltage Range ...

Page 5

Electrical Specifications VCC = 12V, T ENT = L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software description section for I access to the system. (Continued) PARAMETER LINEAR REGULATOR Drop-out Voltage DSQIN PIN DSQIN ...

Page 6

Functional Pin Description (Continued) SYMBOL VCC Main power supply to the chip. GATE This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET. This output is actively ...

Page 7

Simultaneously the overload flag (OLF) bit of the system register is set to HIGH. After this time has elapsed, the output is resumed for a time T ON the device output will be current limited to between 500mA and ...

Page 8

Byte Format Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the ...

Page 9

Received Data ( Bus Read Mode The ISL6421A can provide to the master a copy of the 2 System Register information via the I The read mode is Master activated by sending the chip address with R/W ...

Page 10

Typical Performance Curves 89 88 18. 14. 50.0 150.0 250.0 350.0 I (mA) OUT FIGURE 4. EFFICIENCY vs LOAD CURRENT 22kHz TONE (0.1V/DIV) 10µs/DIV FIGURE 6. 22kHz TONE VOUT (20mV/DIV) VPWM (20mV/DIV) 2µs/DIV ...

Page 11

Typical Performance Curves VOUT (1V/DIV) VPWM (1V/DIV) IOUT (0.2A/DIV) 0.5ms/DIV FIGURE 10. DYNAMIC RESPONSE VOUT = 19.0V VGATE (2V/DIV) VDRAIN (10V/DIV) 2µs/DIV FIGURE 12. GATE AND DRAIN WAVEFORMS VOUT = 19.0V 11 ISL6421A (Continued) VOUT (1V/DIV) VPWM (1V/DIV) IOUT (0.2A/DIV) ...

Page 12

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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