MCBSTM32EXL Keil, MCBSTM32EXL Datasheet

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
June 2009
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx, STM32F102xx, STM32F103xx and
STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,
STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as
STM32F10xxx throughout the document, unless otherwise specified.
The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low-
and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx
connectivity line datasheet.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical
Reference Manual.
Related documents
Available from www.arm.com:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf
Available from www.st.com:
Cortex™-M3 Technical Reference Manual, available from:
STM32F101xx STM32F103xx datasheets
STM32F10xxx Flash programming manual
and STM32F107xx advanced ARM-based 32-bit MCUs
Doc ID 13902 Rev 9
Reference manual
RM0008
www.st.com
1/995

Related parts for MCBSTM32EXL

MCBSTM32EXL Summary of contents

Page 1

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced ARM-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and ...

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Contents Contents 1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.1 ...

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RM0008 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 6.2.7 6.2.8 6.2.9 6.2.10 6.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 8 General-purpose and alternate-function I/Os (GPIOs and AFIOs 138 8.1 GPIO functional description . . . . . . . . . . . . . . ...

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Contents 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 10.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.8 ...

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RM0008 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.3.9 12.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 12.5.11 DUAL DAC 8-bit right aligned data holding register 12.5.12 DAC channel1 data output register (DAC_DOR1 251 12.5.13 DAC channel2 data output register ...

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RM0008 13.4.6 13.4.7 13.4.8 13.4.9 13.4.10 TIM1&TIM8 counter (TIMx_CNT 311 13.4.11 TIM1&TIM8 ...

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Contents 14.4 TIMx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 15.4.8 15.4.9 16 Real-time clock (RTC ...

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Contents 18.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 20 Secure digital input/output interface (SDIO 456 20.1 SDIO main features . . . . . . . . ...

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Contents 20.7.1 20.7.2 20.7.3 20.7.4 20.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 21.5.2 21.5.3 21.5.4 22 Controller area network (bxCAN 542 22.1 ...

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Contents 23 Serial peripheral interface (SPI 586 23.1 SPI introduction ...

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RM0008 23.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 25.3.4 25.3.5 25.3.6 25.3.7 25.3.8 25.3.9 25.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 674 25.3.11 Smartcard . . ...

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RM0008 26.5 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 26.15.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 27.7 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 29.8.6 29.9 AHB-AP (AHB access port) - valid for both JTAG-DP or SW- 965 29.10 Core debug . . . . . . . . . . . . . . . . ...

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RM0008 List of tables Table 1. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 49. ETH remapping ...

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RM0008 Table 100. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 152. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 Table 202. Packet request (8-bits ...

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List of figures List of figures Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 Figure 49. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 101. Counter timing diagram with prescaler division change from 323 Figure 102. Counter timing diagram, internal ...

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RM0008 preloaded ...

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List of figures Figure 203. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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RM0008 Figure 255. IrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 307. System time update using the Fine correction method 875 ...

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RM0008 1 Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) read-only (r) write-only (w) read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ ...

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Memory and bus architecture 2 Memory and bus architecture 2.1 System architecture In low-, medium- and high-density devices, the main system consists of: ● Four masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 ...

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RM0008 In connectivity line devices the main system consists of: ● Five masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA ● Three slaves: – Internal SRAM – Internal ...

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Memory and bus architecture DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex™-M3 core (peripherals ...

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RM0008 2.3 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 1 STM32F10xxx devices. Table 1. Register boundary addresses Boundary address 0x5000 0000 - 0x5000 03FF 0x4003 0000 - 0x4FFF FFFF ...

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Memory and bus architecture Table 1. Register boundary addresses (continued) Boundary address 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - ...

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RM0008 2.3.2 Bit banding The Cortex™-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region ...

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Memory and bus architecture 2.3.3 Embedded Flash memory The high-performance Flash memory module has the following key features: ● Density 512 Kbytes ● Memory organization: the Flash memory is organized as a main block and an information ...

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RM0008 Table 2. Flash module organization (low-density devices) (continued) Block Flash memory interface registers Table 3. Flash module organization (medium-density devices) Block Main memory Information block Flash memory interface registers Name FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 ...

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Memory and bus architecture Table 4. Flash module organization (high-density devices) Block Main memory Information block Flash memory interface registers 46/995 Name Page 0 0x0800 0000 - 0x0800 07FF Page 1 0x0800 0800 - 0x0800 0FFF Page 2 0x0800 1000 ...

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RM0008 Table 5. Flash module organization (connectivity line devices) Block Main memory Information block Flash memory interface registers Note: For further information on the Flash memory interface registers, please refer to the STM32F10xxx Flash programming manual. Reading the Flash memory ...

Page 48

Memory and bus architecture Note: 1 These options should be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: zero wait state, ...

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RM0008 The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a Reset the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode. ...

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CRC calculation unit 3 CRC calculation unit Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges ...

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RM0008 3.3 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ● holds ...

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CRC calculation unit 3.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved Bits 31:8 Reserved Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for ...

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RM0008 4 Power control (PWR) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 ...

Page 54

Power control (PWR) 4.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. ● The ADC voltage supply input ...

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RM0008 Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with ...

Page 56

Power control (PWR) Figure 5. Power on reset/power down reset waveform V DD Reset 4.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V selected by the PLS[2:0] bits in the The PVD is enabled by ...

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RM0008 4.3 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example ...

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Power control (PWR) 4.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks ...

Page 59

RM0008 Table 9. Sleep-now Sleep-now mode Mode entry Mode exit Wakeup latency Table 10. Sleep-on-exit Sleep-on-exit Mode entry Mode exit Wakeup latency 4.3.4 Stop mode The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. ...

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Power control (PWR) In Stop mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be ...

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RM0008 switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Entering Standby mode Refer to Table 12 In Standby mode, the following features can be selected by programming individual control ...

Page 62

Power control (PWR) Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is ...

Page 63

RM0008 Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and ...

Page 64

Power control (PWR) 4.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read ...

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RM0008 4.4.3 PWR register map The following table summarizes the PWR registers. Table 13. PWR register map and reset values Offset Register PWR_CR 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Table 1 on page 41 Reserved Reserved for ...

Page 66

Backup registers (BKP) 5 Backup registers (BKP) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges ...

Page 67

RM0008 5.3 BKP functional description 5.3.1 Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from from depending on the TPAL bit in the detection event resets all ...

Page 68

Backup registers (BKP) 5.4 BKP registers Refer to Section 1.1 on page 37 5.4.1 Backup data register x (BKP_DRx ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 ...

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RM0008 Bit 6:0 CAL[6:0]: Calibration value This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock ...

Page 70

Backup registers (BKP) Bit 8 TEF: Tamper event flag This bit is set by hardware when a Tamper event is detected cleared by writing 1 to the CTE bit Tamper event 1: A Tamper event occurred ...

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RM0008 Table 14. BKP register map and reset values (continued) Offset Register BKP_DR7 0x1C Reset value BKP_DR8 0x20 Reset value BKP_DR9 0x24 Reset value BKP_DR10 0x28 Reset value BKP_RTCCR 0x2 Reset value BKP_CR 0x30 Reset value BKP_CSR 0x34 Reset value ...

Page 72

Backup registers (BKP) Table 14. BKP register map and reset values (continued) Offset Register BKP_DR20 0x64 Reset value BKP_DR21 0x68 Reset value BKP_DR22 0x6C Reset value BKP_DR23 0x70 Reset value BKP_DR24 0x74 Reset value BKP_DR25 0x78 Reset value BKP_DR26 0x7C ...

Page 73

RM0008 Table 14. BKP register map and reset values (continued) Offset Register BKP_DR37 0xA8 Reset value BKP_DR38 0xAC Reset value 0xB0 BKP_DR39 Reset value BKP_DR40 0xB4 Reset value 0xB8 BKP_DR41 Reset value BKP_DR42 0xBC Reset value Refer to Table 1 ...

Page 74

Low-, medium- and high-density reset and clock control (RCC) 6 Low-, medium- and high-density reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices ...

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RM0008 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of ...

Page 76

Low-, medium- and high-density reset and clock control (RCC) 6.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following ...

Page 77

RM0008 Figure 8. Clock tree 8 MHz HSI RC OSC_OUT 4-16 MHz HSE OSC OSC_IN OSC32_IN LSE OSC 32.768 kHz OSC32_OUT LSI RC 40 kHz Main Clock Output MCO 1. When the HSI is used as a PLL clock input, ...

Page 78

Low-, medium- and high-density reset and clock control (RCC the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, ...

Page 79

RM0008 External crystal/ceramic resonator (HSE crystal) The MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in characteristics section of the datasheet for more ...

Page 80

Low-, medium- and high-density reset and clock control (RCC) If the USB interface is used in the application, the PLL must be programmed to output MHz. This is needed to provide a 48 MHz USBCLK. 6.2.4 LSE ...

Page 81

RM0008 Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture ...

Page 82

Low-, medium- and high-density reset and clock control (RCC) The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work ...

Page 83

RM0008 6.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access Reserved HSICAL[7: ...

Page 84

Low-, medium- and high-density reset and clock control (RCC) Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or Standby mode. This bit cannot ...

Page 85

RM0008 Bits 31:27 Reserved, always read as 0. Bits 26:24 MCO: Microcontroller clock output Set and cleared by software. 0xx: No clock 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by ...

Page 86

Low-, medium- and high-density reset and clock control (RCC) Bits 14:14 ADCPRE: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: ...

Page 87

RM0008 Bits 1:0 SW: System clock switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly ...

Page 88

Low-, medium- and high-density reset and clock control (RCC) Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear ...

Page 89

RM0008 Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit clock ready interrupt caused by the external 4-25 MHz oscillator ...

Page 90

Low-, medium- and high-density reset and clock control (RCC) Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI 1 reset Set and cleared by software ...

Page 91

RM0008 Bit 2 IOPARST: I/O port A reset Set and cleared by software effect 1: Reset I/O port A Bit 1 Reserved, always read as 0. Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. ...

Page 92

Low-, medium- and high-density reset and clock control (RCC) Bit 23 USBRST: USB reset Set and cleared by software effect 1: Reset USB Bit 22 I2C2RST: I2C 2 reset Set and cleared by software effect 1: ...

Page 93

RM0008 Bit 5 TIM7RST: Timer 7 reset Set and cleared by software effect 1: Reset timer 7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software effect 1: Reset timer 6 Bit 3 TIM5RST: ...

Page 94

Low-, medium- and high-density reset and clock control (RCC) Bit 10 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO clock disabled 1: SDIO clock enabled Bits 9 Reserved, always read as 0. Bit 8 FSMCEN: FSMC clock ...

Page 95

RM0008 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on ...

Page 96

Low-, medium- and high-density reset and clock control (RCC) Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: I/O port G clock ...

Page 97

RM0008 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. ...

Page 98

Low-, medium- and high-density reset and clock control (RCC) Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled Bit 21 I2C1EN: I2C 1 clock enable Set and ...

Page 99

RM0008 Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled ...

Page 100

Low-, medium- and high-density reset and clock control (RCC) Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared ...

Page 101

RM0008 6.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0  wait state  3, word, half-word and byte access Wait states are inserted in case ...

Page 102

Low-, medium- and high-density reset and clock control (RCC) Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit reset from NRST pin occurred ...

Page 103

RM0008 Table 15. RCC register map and reset values (continued) Offset Register RCC_AHBENR 0x014 Reset value 0x018 RCC_APB2ENR Reset value RCC_APB1ENR 0x01C Reset value 0 0 RCC_BDCR 0x020 Reset value RCC_CSR 0x024 Reset value Refer to ...

Page 104

Connectivity line devices: reset and clock control (RCC) 7 Connectivity line devices: reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, ...

Page 105

RM0008 Low-power management reset There are two ways to generate a low-power management reset: 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a ...

Page 106

Connectivity line devices: reset and clock control (RCC) 7.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following two ...

Page 107

RM0008 Figure 11. Clock tree OSC32_IN 32.768 kHz OSC32_OUT XT1 to MCO OSC_IN OSC_OUT MCO Ethernet PHY ETH_MII_TX_CLK ETH_MII_RX_CLK 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is ...

Page 108

Connectivity line devices: reset and clock control (RCC) Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is ...

Page 109

RM0008 Figure 12. HSE/ LSE clock sources Clock source External clock Crystal/ceramic resonators External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency MHz. You select this ...

Page 110

Connectivity line devices: reset and clock control (RCC) Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T After ...

Page 111

RM0008 External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the domain control register with ...

Page 112

Connectivity line devices: reset and clock control (RCC) 7.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator ...

Page 113

RM0008 7.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock ...

Page 114

Connectivity line devices: reset and clock control (RCC) Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF 1: PLL3 ON Bit 27 PLL2RDY: PLL2 ...

Page 115

RM0008 Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 3-25MHz oscillator when entering Stop or Standby mode. This bit can not be reset if the external 3-25 MHz oscillator ...

Page 116

Connectivity line devices: reset and clock control (RCC) Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by ...

Page 117

RM0008 Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by ...

Page 118

Connectivity line devices: reset and clock control (RCC) Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of ...

Page 119

RM0008 Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to ...

Page 120

Connectivity line devices: reset and clock control (RCC) Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator cleared by software setting the CSSC bit. 0: ...

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RM0008 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access USART1 SPI1 TIM1 RST RST RST Res. ...

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Connectivity line devices: reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. ...

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RM0008 Bit 27 BKPRST: Backup interface reset Set and cleared by software effect 1: Reset backup interface Bit 26 CAN2RST: CAN2 reset Set and cleared by software effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset ...

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Connectivity line devices: reset and clock control (RCC) Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software effect 1: Reset window watchdog Bits 10:6 Reserved, always read as 0. ...

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RM0008 7.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access ETHM ETHM OTGF ACTX ACEN SEN ...

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Connectivity line devices: reset and clock control (RCC) Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode ...

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RM0008 Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface ...

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Connectivity line devices: reset and clock control (RCC) 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a ...

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RM0008 Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled ...

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Connectivity line devices: reset and clock control (RCC) Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared ...

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RM0008 Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, always read as 0. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the ...

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Connectivity line devices: reset and clock control (RCC) 7.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0  wait state  3, word, half-word and byte ...

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RM0008 Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags effect 1: Clear the reset flags Bits 23:2 Reserved, always read as 0. Bit 1 LSIRDY: Internal low speed oscillator ready Set and ...

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Connectivity line devices: reset and clock control (RCC) 7.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access PLL3MUL[3:0] ...

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RM0008 Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock ...

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Connectivity line devices: reset and clock control (RCC) Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as ...

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RM0008 Table 16. RCC register map and reset values (continued) Offset Register RCC_AHBENR 0x014 Reset value 0x018 RCC_APB2ENR Reset value RCC_APB1ENR Reser 0x01C ved Reset value 0 0 RCC_BDCR 0x020 Reset value RCC_CSR 0x024 Reset value ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and ...

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RM0008 Figure 13. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral Alternate Function Input Read Write Read/write From on-chip peripheral Figure 14. Basic structure of a five-volt tolerant I/O port bit Analog Input To on-chip ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 17. Port bit configuration table Configuration mode General purpose output Alternate Function output Input Table 18. Output MODE bits 8.1.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are ...

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RM0008 or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be modified. 8.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.1.7 Input configuration When the I/O Port is programmed as Input: ● The Output Buffer is disabled ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are activated ...

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RM0008 Figure 16. Output configuration Read Write Read/write potential specific to five-volt tolerant I/Os and different from V DD_FT 8.1.9 Alternate function configuration When the I/O Port is programmed as Alternate Function: ● The Output Buffer ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 17. Alternate function configuration Alternate Function Input To on-chip peripheral Read Write Read/write From on-chip Alternate Function Output peripheral potential specific to five-volt tolerant I/Os and different from ...

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RM0008 8.1.11 Peripherals’ GPIO configurations Table 19 to Table 29 Table 19. Advanced timers TIM1/TIM8 TIM1/8 pinout TIM1/8_CHx TIM1/8_CHxN TIM1/8_BKIN TIM1/8_ETR Table 20. General-purpose timers TIM2/3/4/5 TIM2/3/4 pinout TIM2/3/4/5_CHx TIM2/3/4/5_ETR Table 21. USARTs USART pinout USARTx_TX USARTx_RX USARTx_CK USARTx_RTS USARTx_CTS ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 22. SPI (continued) SPI pinout Full duplex / Master Full Duplex / slave SPIx_MISO Simplex bidirectional data wire / Master Simplex bidirectional data wire/ Slave Hardware Master /Slave SPIx_NSS Hardware Master/ NSS ...

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RM0008 Table 27. SDIO SDIO pinout SDIO_CK SDIO_CMD SDIO[D7:D0] The GPIO configuration of the ADC inputs should be analog. Figure 19. ADC / DAC ADC/DAC pin ADC/DAC Table 28. FSMC FSMC pinout FSMC_A[25:0] FSMC_D[15:0] FSMC_CK FSMC_NOE FSMC_NWE FSMC_NE[4:1] FSMC_NCE[3:2] FSMC_NCE4_1 ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2 GPIO registers Refer to Section 1.1 on page 37 8.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0] MODE7[1:0] CNF6[1:0] rw ...

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RM0008 8.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1: CNF11[1:0] MODE11[1:0] CNF10[1: ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ...

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RM0008 8.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 Bits 31:16 Reserved Bits 15:0 ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock ...

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RM0008 8.3.3 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 30. CAN1 ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the configuration register Table 33. Debug port mapping SWJ _CFG ...

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RM0008 Table 37. ADC2 external trigger regular conversion alternate function remapping Alternate function ADC2 external trigger regular conversion 1. Remap available only for high-density devices. 8.3.7 Timer alternate function remapping Timer 4 channels can be remapped from ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 41. TIM2 alternate function remapping Alternate function (2) TIM2_CH1_ETR TIM2_CH2 TIM2_CH3 TIM2_CH4 1. Remap not available on 36-pin package. 2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at ...

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RM0008 Table 44. USART2 remapping Alternate functions USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK 1. Remap available only for 100-pin and 144-pin packages. Table 45. USART1 remapping Alternate function USART1_TX USART1_RX 8.3.9 I2C1 alternate function remapping Refer to AF remap and debug ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 48. SPI3 remapping Alternate function SPI3_NSS SPI3_SCK SPI3_MISO SPI3_MOSI 8.3.12 Ethernet alternate function remapping Refer to AF remap and debug I/O configuration register only in connectivity line devices. Table 49. ETH remapping ...

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RM0008 Bits 6:4 PORT[2:0]: Port selection Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal. Note: The EVENTOUT signal output capability is not extended to ports PF and PG. 000: PA selected 001: PB ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger regular conversion. When this bit is reset, ...

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RM0008 Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports remap (NSS/PA4, ...

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RM0008 Bit 23 MII_RMII_SEL: MII or RMII selection This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY. 0: Configure Ethernet MAC for connection with an MII ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, ...

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RM0008 Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 EXTI11[3: Bits 31:16 Reserved Bits ...

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RM0008 8.5 GPIO and AFIO register maps Refer to Table 1 on page 41 the GPIO and AFIO register map and the reset values. Table 50. GPIO register map and reset values Offset Register CNF7 MODE7 CNF6 GPIOx_CRL [1:0] [1:0] ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 51. AFIO register map and reset values (continued) Offset Register AFIO_EXTICR3 0x10 Reset value AFIO_EXTICR4 0x14 Reset value Refer to Table 1 on page 41 168/995 EXTI11[3:0] Reserved 0 0 EXTI15[3:0] Reserved ...

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RM0008 9 Interrupts and events Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 ...

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Interrupts and events Table 52. Vector table for connectivity line devices (continued) Type of priority -1 fixed 0 settable 1 settable 2 settable - - 3 settable 4 settable - - 5 settable 6 settable 0 7 settable 1 8 ...

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RM0008 Table 52. Vector table for connectivity line devices (continued) Type of priority 22 29 settable 23 30 settable 24 31 settable 25 32 settable 26 33 settable 27 34 settable 28 35 settable 29 36 settable 30 37 settable ...

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Interrupts and events Table 52. Vector table for connectivity line devices (continued) Type of priority 59 66 settable 60 67 settable 61 68 settable 62 69 settable 63 70 settable 64 71 settable 65 72 settable 66 73 settable 67 ...

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RM0008 Table 53. Vector table for other STM32F10xxx devices (continued) Type of priority 3 10 settable 4 11 settable 5 12 settable 6 13 settable 7 14 settable 8 15 settable 9 16 settable 10 17 settable 11 18 settable ...

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Interrupts and events Table 53. Vector table for other STM32F10xxx devices (continued) Type of priority 35 42 settable 36 43 settable 37 44 settable 38 45 settable 39 46 settable 40 47 settable 41 48 settable 42 49 settable 43 ...

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RM0008 9.2.1 Main features The EXTI controller main features are the following: ● Independent trigger and mask on each interrupt/event line ● Dedicated status bit for each interrupt line ● Generation software event/interrupt requests ● Detection ...

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Interrupts and events In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to 9.2.4 Functional description To generate the interrupt, the interrupt line should be configured ...

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RM0008 Figure 21. External interrupt/event GPIO mapping 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. Refer to (RCC_APB2ENR) enable register (RCC_APB2ENR) The four other EXTI lines are ...

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Interrupts and events 9.3 registers EXTI Refer to Section 1.1 on page 37 9.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR15 MR14 MR13 MR12 MR11 ...

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RM0008 9.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR15 TR14 TR13 TR12 TR11 Bits 31:20 Reserved, must be kept ...

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Interrupts and events 9.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER ...

Page 181

RM0008 9.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Table 54. External interrupt/event controller register map and ...

Page 182

DMA controller (DMA) 10 DMA controller (DMA) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges ...

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RM0008 Figure 22. DMA block diagram in connectivity line devices Cortex-M3 DMA1 Ch.1 Ch.2 Ch.7 Arbiter AHB Slave DMA2 Ch.1 Ch.2 Ch.5 Arbiter AHB Slave Ethernet MAC USB OTG FS 1. The DMA2 controller is available only in high-density and ...

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DMA controller (DMA) release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: ● The loading of data from the peripheral data register or a location ...

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RM0008 transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after ...

Page 186

DMA controller (DMA) If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once ...

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RM0008 not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: ● To write the ...

Page 188

DMA controller (DMA) 10.3.7 DMA request mapping DMA1 controller The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one request must be enabled at a ...

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RM0008 Table 57. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 ADC1 ADC1 2 SPI/I S SPI1_RX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX TIM1 TIM1_CH1 TIM2 TIM2_CH3 TIM2_UP TIM3 TIM3_CH3 TIM4 TIM4_CH1 ...

Page 190

DMA controller (DMA) Figure 24. DMA2 request mapping Peripheral request signals TIM5_CH4 TIM5_TRIG TIM8_CH3 TIM8_UP SPI/I2S3_RX TIM8_CH4 TIM8_TRIG TIM8_COM TIM5_CH3 TIM5_UP SPI/I2S3_TX TIM8_CH1 UART4_RX TIM6_UP/DAC_Channel1 TIM5_CH2 SDIO TIM7_UP/DAC_Channel2 ADC3 TIM8_CH2 TIM5_CH1 UART4_TX Table 58 lists the DMA2 requests for each ...

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RM0008 10.4 DMA registers Refer to Section 1.1 on page 37 Note: In the following registers, all bits relative to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels. 10.4.1 DMA interrupt status register (DMA_ISR) ...

Page 192

DMA controller (DMA) 10.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF 7 Reserved CTEIF CHTIF CTCIF CGIF CTEIF ...

Page 193

RM0008 10.4.3 DMA channel x configuration register (DMA_CCRx ..7) Address offset: 0x08 + 20d × Channel number Reset value: 0x0000 0000 MEM2 PL[1:0] MSIZE[1:0] MEM Res. rw ...

Page 194

DMA controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read ...

Page 195

RM0008 10.4.5 DMA channel x peripheral address register (DMA_CPARx ..7) Address offset: 0x10 + dx20 × Channel number Reset value: 0x0000 0000 This register must not be written when the channel is enabled ...

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DMA controller (DMA) 10.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 59. DMA register map and reset values Offset Register DMA_ISR 0x000 Reserved Reset value DMA_IFCR 0x004 Reserved Reset value DMA_CCR1 ...

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RM0008 Table 59. DMA register map and reset values (continued) Offset Register DMA_CPAR4 0x04C Reset value DMA_CMAR4 0x050 Reset value 0x054 DMA_CCR5 0x058 Reset value DMA_CNDTR5 0x05C Reset value DMA_CPAR5 0x060 Reset ...

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Analog-to-digital converter (ADC) 11 Analog-to-digital converter (ADC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges ...

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RM0008 11.2 ADC main features ● 12-bit resolution ● Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event ● Single and continuous conversion modes ● Scan mode for automatic conversion of channel 0 to channel ...

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Analog-to-digital converter (ADC) Figure 25. Single ADC block diagram V REF+ V REF- V DDA V SSA ADCx_IN0 ADCx_IN1 ADCx_IN15 Temp. sensor TIM1_TRGO TIM1_CH4 TIM2_TRGO TIM2_CH1 TIM3_CH4 TIM4_TRGO EXTI_15 TIM8_CH4 ADCx-ETRGINJ_REMAP bit EXTI_11 TIM8_TRGO 1. ADC3 has regular and injected ...

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