LIS302DLTR STMicroelectronics, LIS302DLTR Datasheet
LIS302DLTR
Specifications of LIS302DLTR
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LIS302DLTR Summary of contents
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... Table 1. Device summary Part number LIS302DL LIS302DLTR LIS302DLTR8 October 2008 The LIS302DL has dynamically user selectable full scales of ± 2g/± 8g and it is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz. A self-test capability allows the user to check the functioning of the sensor in the final application ...
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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Block ...
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LIS302DL 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS302DL List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 47. CLICK_CFG (38h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS302DL List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection CHARGE AMPLIFIER Z+ A/D MUX CONVERTER Z- ...
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LIS302DL Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins GND 0V supply Reserved Connect to Vdd GND 0V supply GND 0V supply ...
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Mechanical and electrical specifications 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics (All the parameters are specified @ Vdd=2 25°C unless otherwise noted) Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs ...
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LIS302DL 2.2 Electrical characteristics Table 4. Electrical characteristics (All the parameters are specified @ Vdd=2 25°C unless otherwise noted) Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Idd Supply current Current consumption in IddPdn power-down mode ...
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Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - Serial Peripheral Interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS ...
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LIS302DL 2 2.3 inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) ...
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Mechanical and electrical specifications 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not ...
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LIS302DL 2.5.2 Zero-g level Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g ...
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Functionality 3 Functionality The LIS302DL is a ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...
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LIS302DL 4 Application hints Figure 5. LIS302DL electrical connection Vdd 10uF 100nF GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) ...
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Digital interfaces 5 Digital interfaces The registers embedded inside the LIS302DL may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are ...
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LIS302DL 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. ...
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Digital interfaces Table 13. Transfer when Master is receiving (reading) one byte of data from slave Master ST SAD + W Slave Table 14. ransfer when master is receiving (reading) Master ST SAD + W Slave Table 15. Multiple bytes ...
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LIS302DL Figure 6. Read & write protocol CS SPC SDI SDO CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the ...
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Digital interfaces 5.2.1 SPI Read Figure 7. SPI Read protocol CS SPC SDI SDO The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. ...
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LIS302DL The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When ...
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Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 16. Register address map Name Reserved (Do not modify) Who_Am_I Reserved (Do not modify) ...
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LIS302DL Table 16. Register address map (continued) Name CLICK_THSZ CLICK_TimeLimit CLICK_Latency CLICK_Window Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded ...
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Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the ...
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LIS302DL Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. ...
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Register description Table 22. High pass filter cut-off frequency configuration HP_coeff2 7.4 CTRL_REG3 [Interrupt CTRL register] (22h) Table 23. CTRL_REG3 (22h) register IHL PP_OD Table 24. CTRL_REG3 (22h) register description IHL Interrupt active high, low. Default ...
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LIS302DL 7.6 STATUS_REG (27h) Table 26. STATUS_REG (27h) register ZXYOR ZOR Table 27. STATUS_REG (27h) register desription X, Y and Z axis data overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has over written the ...
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Register description 7.9 OUT_Z (2Dh) Table 30. OUT_Z (2Dh) register ZD7 ZD6 Z axis output data. 7.10 FF_WU_CFG_1 (30h) Table 31. FF_WW_CFG_1 (30h) register AOI LIR Table 32. FF_WW_CFG_1(30h) register description And/or combination of Interrupt events. Default value: 0 AOI ...
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LIS302DL 7.11 FF_WU_SRC_1 (31h) Table 33. FF_WU_SRC_1 (31h) register X IA Table 34. FF_WU_SRC_1 (31h) register description Interrupt active. Default value (0: no interrupt has been generated; 1: one ore more interrupt has been generated) Z high. Default ...
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Register description 7.13 FF_WU_DURATION_1 (33h) Table 37. FF_WU_DURATION_1 (33h) register D7 D6 Table 38. FF_WU_DURATION_1 (33h) register description D7-D0 Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 ...
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LIS302DL 7.15 FF_WU_SRC_2 (35h) Table 41. FF_WU_SRC_2 (35h) register X IA Table 42. FF_WU_SRC_2 (35h) register description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated ...
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Register description Table 46. FF_WU_DURATION_2 (37h) register description D7-D0 Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ...
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LIS302DL Table 51. CLICK_SRC (39h) register description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Double_Z Double click on Z axis event. Default value: 0 (0: no ...
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Register description 7.23 CLICK_Latency (3Eh) Table 57. CLICK_Latency (3Eh) register Lat7 Lat6 From 0 to 255 msec with step of 1 msec. 7.24 CLICK_Window (3Fh) Table 58. CLICK_Window (3Fh) register Win7 Win6 From 0 to 255 msec with step of ...
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LIS302DL 8 Typical performance characteristics 8.1 Mechanical characteristics at 25°C Figure 12. X axis 0-g level at 2. −150 −100 −50 0 Zero−g Level Offset [mg] Figure 14. Y axis 0-g level at ...
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Typical performance characteristics 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range Figure 18. X axis 0-g level change vs temperature at 2. −3 −2 −1 0 0−g ...
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LIS302DL 8.3 Electro-mechanical characteristics at 25°C Figure 24. Current consumption in normal mode at 2. 200 220 240 260 280 300 Current consumption [uA] Figure 25. Current consumption in power 320 340 360 ...
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Package information 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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LIS302DL 10 Revision history Table 59. Document revision history Date 3-Oct-2006 6-Feb-2007 25-Oct-2007 21-Oct-2008 Revision 1 Initial release. Added functions and registers information and typical performance 2 characteristics Added interfaces timing characteristics and global datasheet review 3 to improved readability ...
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