LIS331DLFTR STMicroelectronics, LIS331DLFTR Datasheet
LIS331DLFTR
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LIS331DLFTR Summary of contents
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... Table 1. Device summary Order codes Temperature range [° C] LIS331DLF LIS331DLFTR July 2009 MEMS digital output motion sensor belonging to the “nano” family, with digital I serial interface standard output. The device features ultra low-power operational modes that allow advanced power saving and smart sleep to wake-up functions ...
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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block ...
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LIS331DLF 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331DLF Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331DLF 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS X+ Y+ CHARGE AMPLIFIER Z+ A/D MUX ...
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Block diagram and pin description Table 2. Pin description Pin 8/38 Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected ...
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LIS331DLF 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Dres Device resolution Sensitivity change vs TCSo temperature ...
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Mechanical and electrical specifications 2.2 Electrical characteristics Table 4. Electrical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Current consumption Idd in normal mode Current ...
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LIS331DLF 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) ...
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Mechanical and electrical specifications 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock ...
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LIS331DLF 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by ...
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LIS331DLF 3 Functionality The LIS331DLF is a “nano”, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...
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Application hints 4 Application hints Figure 5. LIS331DLF electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO ...
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LIS331DLF 5 Digital interfaces The registers embedded inside the LIS331DLF may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped ...
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... LSb is ‘1’ (address 0101001b) else if SA0 pad is connected to ground, LSb value is ‘0’ (address 0101000b). This solution permits to connect and address two different accelerometers to the same I Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse ...
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LIS331DLF Table 12. Transfer when master is writing multiple bytes to slave: Master ST Slave Table 13. Transfer when master is receiving (reading) one byte of data from slave: Master ST SAD + W Slave Table 14. Transfer when Master ...
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Digital interfaces Figure 6. Read and write protocol CS SPC SDI SDO CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at ...
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LIS331DLF The SPI read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When ...
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Digital interfaces Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG4. ...
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LIS331DLF 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Name Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG1 ...
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Register mapping Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory ...
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LIS331DLF 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...
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Register description Table 19. Power mode and low-power output data rate configurations PM2 PM1 Table 20. Normal-mode output data rate configurations and low-pass cut-off frequencies (1) DR1 “11” bit ...
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LIS331DLF Table 22. CTRL_REG2 description (continued) High pass filter enabled for interrupt 1 source. Default value: 0 HPen1 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 HPCF1, HPCF0 (00: HPc=8; 01: HPc=16; 10: ...
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Register description 7.4 CTRL_REG3 [Interrupt CTRL register] (22h) Table 25. CTRL_REG3 register IHL PP_OD Table 26. CTRL_REG3 description Interrupt active high, low. Default value: 0 IHL (0: active high; 1: active low) Push-pull/Open drain selection on interrupt pad. Default value ...
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LIS331DLF Table 29. CTRL_REG4 description Full-scale selection. Default value: 00. FS1, FS0 (00: ±2 g; 01: ±4 g; 11: ±8 g) Self-test sign. Default value: 00. STsign (0: self-test plus; 1 self-test minus) Self-test enable. Default value (0: ...
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Register description 7.9 STATUS_REG (27h) Table 34. STATUS_REG register ZYXOR ZOR Table 35. STATUS_REG description X, Y and Z axis data overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous one before ...
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LIS331DLF 7.13 INT1_CFG (30h) Table 36. INT1_CFG register AOI 6D Table 37. INT1_CFG description AND/OR combination of Interrupt events. Default value: 0. AOI (See 6 direction detection function enable. Default value (See Enable interrupt generation on Z high ...
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Register description 7.14 INT1_SRC (31h) Table 39. INT1_SRC register 0 IA Table 40. INT1_SRC description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 ...
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LIS331DLF Table 44. INT2_DURATION description bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 7.17 INT2_CFG (34h) Table 45. INT2_CFG ...
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Register description Table 47. Interrupt mode configuration (continued) AOI 1 1 7.18 INT2_SRC (35h) Table 48. INT2_SRC register 0 IA Table 49. INT2_SRC description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more ...
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LIS331DLF 7.20 INT2_DURATION (37h) Table 52. INT2_DURATION register 0 D6 Table 53. INT2_DURATION description bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend ...
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Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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LIS331DLF 9 Revision history Table 54. Document revision history Date 16-Oct-2008 03-Nov-2008 21-Nov-2008 10-Jul-2009 Revision 1 Initial release Table 10, 15 have been updated Table 4 on page 10 3 Updated Table 3 on page Updated: page 12, ...
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