LIS331HHTR STMicroelectronics, LIS331HHTR Datasheet
LIS331HHTR
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LIS331HHTR Summary of contents
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... Table 1. Device summary Order codes Temperature range [° C] LIS331HH LIS331HHTR October 2009 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. MEMS digital output motion sensor accelerometer belonging to the “nano” family, with ...
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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Block ...
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LIS331HH 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331HH Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331HH 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS X+ Y+ CHARGE AMPLIFIER Z+ A/D MUX ...
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Block diagram and pin description Table 2. Pin description Pin 8/37 Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected ...
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LIS331HH 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs TCSo temperature g Typical zero- ...
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Mechanical and electrical specifications 2.2 Electrical characteristics Table 4. Electrical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Current consumption Idd in normal mode Current ...
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LIS331HH 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) ...
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Mechanical and electrical specifications 2 2.3 inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock ...
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LIS331HH 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by ...
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LIS331HH 3 Functionality The LIS331HH is a “nano”, low-power, high full-scale digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing ...
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Application hints 4 Application hints Figure 5. LIS331HH electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO ...
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LIS331HH 5 Digital interfaces The registers embedded inside the LIS331HH may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped ...
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... LSb is ‘1’ (address 0011001b) else if SA0 pad is connected to ground, LSb value is ‘0’ (address 0011000b). This solution permits to connect and address two different accelerometers to the same I Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse ...
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LIS331HH Table 12. Transfer when master is writing multiple bytes to slave: Master ST Slave Table 13. Transfer when master is receiving (reading) one byte of data from slave: Master ST SAD + W Slave Table 14. Transfer when Master ...
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Digital interfaces Figure 6. Read and write protocol CS SPC SDI SDO CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at ...
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LIS331HH The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When ...
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Digital interfaces Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG4. ...
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LIS331HH 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Name Reserved (do not modify) CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 HP_FILTER_RESET ...
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Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the ...
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LIS331HH Table 18. Power mode and low-power output data rate configurations (continued) PM2 PM1 1 1 Table 19. Normal-mode output data rate configurations and low-pass cut-off frequencies DR1 7.2 CTRL_REG2 (21h) Table 20. CTRL_REG2 register BOOT ...
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Register description inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to ...
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LIS331HH Table 25. CTRL_REG3 description (continued) Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0. LIR2 (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 2 pad control ...
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Register description BDU bit is used to inhibit output registers update between the reading of upper and lower register parts. In default mode (BDU = ‘0’) the lower and upper register parts are updated continuously not sure ...
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LIS331HH Table 33. REFERENCE description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h. This register sets the acceleration value taken as a reference for the high-pass filter output. When filter is turned on (at least one of ...
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Register description 7.10 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis acceleration data. The value is expressed as two’s complement. 7.11 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis acceleration data. The value is expressed as two’s complement. 7.12 INT1_CFG (30h) Table 36. INT1_CFG register AOI ...
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LIS331HH Table 38. Interrupt 1 source configurations AOI 7.13 INT1_SRC (31h) Table 39. INT1_SRC register 0 IA Table 40. INT1_SRC description Interrupt active. Default value (0: no interrupt has been generated; 1: one or ...
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Register description Table 42. INT1_THS description THS6 - THS0 7.15 INT1_DURATION (33h) Table 43. INT1_DURATION register 0 D6 Table 44. INT2_DURATION description bits set the minimum duration of the Interrupt 2 event to be ...
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LIS331HH Table 46. INT2_CFG description Enable interrupt generation on X high event. Default value: 0 XHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default ...
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Register description Reading at this address clears INT2_SRC IA bit (and the interrupt signal on INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option was chosen. 7.18 INT2_THS (36h) Table 50. INT2_THS ...
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LIS331HH 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK ...
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Revision history 9 Revision history Table 54. Document revision history Date 05-Oct-2009 36/37 Revision 1 Initial release Doc ID 16366 Rev 1 LIS331HH Changes ...
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... LIS331HH Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...