LTC6993CDCB-2#TRMPBF Linear Technology, LTC6993CDCB-2#TRMPBF Datasheet - Page 17

IC, TIMERBLOX, SINGLE, 5.5V, DFN6

LTC6993CDCB-2#TRMPBF

Manufacturer Part Number
LTC6993CDCB-2#TRMPBF
Description
IC, TIMERBLOX, SINGLE, 5.5V, DFN6
Manufacturer
Linear Technology
Datasheet

Specifications of LTC6993CDCB-2#TRMPBF

Operating Mode
Monostable
No. Of Timers
1
Clock External Input
No
Supply Voltage Range
2.25V To 5.5V
Digital Ic Case Style
DFN
No. Of Pins
6
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC6993CDCB-2#TRMPBFLTC6993CDCB-2
Manufacturer:
LT
Quantity:
10 000
APPLICATIONS INFORMATION
I
When operating with I
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
I
stop. Under this condition, the output pulse can still be
initiated, but will not terminate until I
the master oscillator starts again.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Settling Time
Following a 2× or 0.5× step change in I
pulse width takes approximately six master clock cycles
(6 • t
An example is shown in Figure 10, using the circuit in
Figure 8.
SET
SET
PULSE WIDTH
< 1.25µA. At approximately 500nA, the oscillator will
Extremes (Master Oscillator Frequency Extremes)
2µs/DIV
MASTER
2V/DIV
5V/DIV
5V/DIV
V
TRIG
CTRL
OUT
LTC6993-1
V
DIVCODE = 0
R
R
t
OUT
+
SET
MOD
) to settle to within 1% of the final value.
= 3.3V
= 3µs AND 6µs
= 200k
Figure 10. Typical Settling Time
= 464k
SET
20µs/DIV
outside of the recommended
SET
69931234 F10
SET
increases and
, the output
Coupling Error
The current sourced by the SET pin is used to bias the in-
ternal master oscillator. The LTC6993 responds to changes
in I
settling time. However, this fast response also makes the
SET pin sensitive to coupling from digital signals, such
as the TRIG input.
Even an excellent layout will allow some coupling between
TRIG and SET. Additional error is included in the speci-
fied accuracy for N
shows that ÷1 supply variation is dependent on coupling
from rising or falling trigger inputs and, to a lesser extent,
output polarity.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
TRIG (or any other fast-edge, wide-swing signal).
SET
almost immediately, which provides excellent
–0.2
–0.4
–0.6
–1.0
–0.8
0.2
1.0
0.8
0.6
0.4
Figure 11. t
0
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
2
R
N
SET
DIV
= 1
= 50k
DIV
3
OUT
= 1 to account for this. Figure 11
LTC6993-3
SUPPLY (V)
Drift vs Supply Voltage
POL = 0
LTC6993-1
POL = 1
4
LTC6993-3
POL = 1
LTC6993-1
5
POL = 0
69931234 F11
6
17
69931234f

Related parts for LTC6993CDCB-2#TRMPBF