LTC6993CDCB-3#TRMPBF Linear Technology, LTC6993CDCB-3#TRMPBF Datasheet - Page 14

• Manufacturer Part Number: LTC6993CDCB-3#TRMPBF
• Description: IC, TIMERBLOX, SINGLE, 5.5V, DFN6
• Manufacturer: Linear Technology

Specifications of LTC6993CDCB-3#TRMPBF

• Operating Mode: Monostable
• No. Of Timers: 1
• Clock External Input: No
• Supply Voltage Range: 2.25V To 5.5V
• Digital Ic Case Style: DFN
• No. Of Pins: 6
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring V
be recognized slowly, as the LTC6993 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
A change in DIVCODE will not be recognized until it is stable,
and will not pass through intermediate codes. A digital
filter is used to guarantee the DIVCODE has settled to a
new value before making changes to the output. However,
if the output pulse is active during the transition, the pulse
width can take on a value between the two settings.
14
t
500mV/DIV
500mV/DIV
DIVCODE
2V/DIV
2V/DIV
2V/DIV
2V/DIV
TRIG
TRIG
OUT
OUT
DIV
DIV
LTC6993-1
V
R
LTC6993-1
V
R
Figure 5a. DIVCODE Change from 0 to 2
Figure 5b. DIVCODE Change from 2 to 0
+
+
= 16 • (∆DIVCODE + 6) • t
SET
SET
= 3.3V
= 3.3V
DIV
= 200k
= 200k
for changes. Changes to DIVCODE will
4µs
256µs
512µs
512µs
200µs/DIV
200µs/DIV
256µs
4µs
MASTER
69931234 F05b
69931234 F05a
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
is held low during this time. The typical value for t
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before an output pulse can be
generated. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V
extend the start-up time.
The DIVCODE setting is recognized at the end of the startup
up. If POL = 1, the output will transition high. Otherwise
(if POL = 0) OUT simply remains low. At this point, the
LTC6993 is ready to respond to rising/falling edges on
the TRIG input.
t
START(TYP)
TRIG
OUT
V
+
Figure 6. Start-Up Timing Diagram
= 500 • t
(TRIG IGNORED)
t
START
MASTER
+
. Less than 100pF will not
POL = 0
POL = 1
DIV
t
):
OUT
START
. The OUT pin
69931234 F06
69931234f
START