LTC6993CDCB-3#TRMPBF Linear Technology, LTC6993CDCB-3#TRMPBF Datasheet - Page 19

IC, TIMERBLOX, SINGLE, 5.5V, DFN6

LTC6993CDCB-3#TRMPBF

Manufacturer Part Number
LTC6993CDCB-3#TRMPBF
Description
IC, TIMERBLOX, SINGLE, 5.5V, DFN6
Manufacturer
Linear Technology
Datasheet

Specifications of LTC6993CDCB-3#TRMPBF

Operating Mode
Monostable
No. Of Timers
1
Clock External Input
No
Supply Voltage Range
2.25V To 5.5V
Digital Ic Case Style
DFN
No. Of Pins
6
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC6993CDCB-3#TRMPBFLTC6993CDCB-3
Manufacturer:
LT
Quantity:
10 000
APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines
The LTC6993 is an accurate monostable multivibrator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 13 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6993. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V
GND pins using a low inductance path. The connection
from C1 to the V
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
+
pin is easily done directly on the top
R2
R1
SET
DIV
V
V
+
+
R
C1
SET
DCB PACKAGE
Figure 13. Supply Bypassing and PCB Layout
TRIG
GND
OUT
R
SET
+
and
TRIG
GND
SET
LTC6993
2. Place all passive components on the top side of the
3. Place R
4. Connect R
5. Use a ground trace to shield the SET pin. This provides
6. Place R1 and R2 close to the DIV pin. A direct, short
OUT
DIV
V
+
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
board. This minimizes trace inductance.
make a direct, short connection. The SET pin is a cur-
rent summing node and currents injected into this pin
directly modulate the output pulse width. Having a short
connection minimizes the exposure to signal pickup.
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
another layer of protection from radiated signals.
connection to the DIV pin minimizes the external signal
coupling.
C1
0.1µF
SET
TRIG
GND
R
SET
SET
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
SET
TSOT-23 PACKAGE
as close as possible to the SET pin and
R1
R2
directly to the GND pin. Using a long path
V
+
R2
OUT
DIV
C1
V
+
69931234 F13
R1
V
+
19
69931234f

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