NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet
NH82801HBM S LB9A
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... Intel I/O Controller Hub 8 (ICH8) Family Datasheet ® – For the Intel 82801HB ICH8, 82801HR ICH8R, 82801HDH ICH8DH, 82801HDO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E I/O Controller Hubs May 2007 Document Number: 313056-003 ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ...
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... Miscellaneous Signals ........................................................................................ 79 ® 2.19 Intel High Definition Audio Link ......................................................................... 80 2.20 Serial Peripheral Interface (SPI) .......................................................................... 81 ® 2.21 Intel Quick Resume Technology (Intel 2.22 Controller Link .................................................................................................. 82 ® 2.23 Intel Quiet System Technology (Desktop Only) ................................................... 83 2.24 General Purpose I/O Signals ............................................................................... 83 2.25 Power and Ground............................................................................................. 86 2 ...
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... SYNC Error Indication .............................................................. 127 5.4.1.8 LFRAME# Usage...................................................................... 127 5.4.1.9 I/O Cycles .............................................................................. 128 5.4.1.10 Bus Master Cycles ................................................................... 128 5.4.1.11 LPC Power Management ........................................................... 128 5.4.1.12 Configuration and Intel 5.5 DMA Operation (D31:F0) .................................................................................. 129 5.5.1 Channel Priority.................................................................................... 129 5.5.1.1 Fixed Priority .......................................................................... 130 5.5.1.2 Rotating Priority ...
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... Registers Associated with Front Side Bus Interrupt Delivery.......... 148 5.9.4.4 Interrupt Message Format ........................................................ 148 5.10 Serial Interrupt (D31:F0) ................................................................................. 149 5.10.1 Start Frame......................................................................................... 149 5.10.2 Data Frames........................................................................................ 150 5.10.3 Stop Frame ......................................................................................... 150 5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150 5.10.5 Data Frame Format .............................................................................. 151 ® Intel ICH8 Family Datasheet 5 ...
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... Power Management ................................................................. 158 5.13 Power Management (D31:F0) ............................................................................ 159 5.13.1 Features .............................................................................................. 159 ® 5.13.2 Intel ICH8 and System Power States ..................................................... 160 5.13.3 System Power Planes ............................................................................ 162 5.13.4 SMI#/SCI Generation ............................................................................ 162 5.13.4.1 PCI Express* SCI .................................................................... 165 5.13.4.2 PCI Express* Hot-Plug ............................................................. 165 5 ...
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... Low) (Mobile Only) ...................................... 182 5.13.11.7Controlling Leakage and Power Consumption during Low-Power States ......................................................... 182 5.13.12Clock Generators.................................................................................. 182 5.13.12.1Clock Control Signals from Intel Synthesizer (Mobile Only) ........................................................ 183 5.13.13Legacy Power Management Theory of Operation ....................................... 183 5.13.13.1APM Power Management (Desktop Only) .................................... 183 5.13.13.2Mobile APM Power Management (Mobile Only) ............................ 183 5 ...
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... SMI Trapping (APM)................................................................. 201 5.16.5 SATA LED ............................................................................................ 201 5.16.6 AHCI Operation .................................................................................... 201 5.16.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................ 202 5.16.8 SGPIO Signals ...................................................................................... 202 5.16.9 External SATA (Intel 5.17 High Precision Event Timers .............................................................................. 203 5.17.1 Timer Accuracy .................................................................................... 203 5.17.2 Interrupt Mapping................................................................................. 203 5 ...
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... Direct Access Security ............................................................. 245 5.23.1.5 Register Access Security .......................................................... 245 5.23.2 SPI Device Compatibility Requirements ................................................... 246 5.23.2.1 Device Requirements for System BIOS Storage Only ................... 246 5.23.2.2 Device Requirements for Intel Firmware ............................................................................... 246 5.23.2.3 Device Requirements for GbE ................................................... 247 5.23.3 Serial Flash Command Set..................................................................... 247 5 ...
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... RP3BA—Root Port 3 Base Address Register............................................... 276 7.1.24 RP4D—Root Port 4 Descriptor Register..................................................... 276 7.1.25 RP4BA—Root Port 4 Base Address Register............................................... 276 ® 7.1.26 HDD—Intel 7.1.27 HDBA—Intel 7.1.28 RP5D—Root Port 5 Descriptor Register..................................................... 277 7.1.29 RP5BA—Root Port 5 Base Address Register............................................... 278 7.1.30 RP6D— ...
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... SID—Subsystem ID Register (Gigabit LAN—D25:F0) ................................. 315 8.1.14 SVID—Subsystem Vendor ID Register (Gigabit LAN—D25:F0) .................... 315 8.1.15 ERBA—Expansion ROM Base Address Register (Gigabit LAN—D25:F0).......................................................................... 316 8.1.16 CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0) .................. 316 ® Intel ICH8 Family Datasheet 11 ...
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... GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) ................................................................................ 335 9.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0) ................................................................................ 335 9.1.23 GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0) ................................................................................ 336 12 ® Intel ICH8 Family Datasheet ...
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... Interrupt Controller I/O MAP (LPC I/F—D31:F0) ....................................... 356 9.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31:F0) ................................................................................ 357 9.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31:F0) ................................................................................ 358 9.4.4 ICW3—Master Controller Initialization Command Word 3 Register (LPC I/F—D31:F0)......................................................... 358 ® Intel ICH8 Family Datasheet 13 ...
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... GEN_PMCON_LOCK—General Power Management Configuration Lock Register ...................................................... 383 9.8.1.5 Cx-STATE_CNF—Cx State Configuration Register (PM—D31:F0) (Mobile Only) ..................................................... 384 9.8.1.6 C4-TIMING_CNT—C4 Timing Control Register (PM—D31:F0) (Mobile Only) ..................................................... 385 9.8.1.7 BM_BREAK_EN Register (PM—D31:F0) (Mobile Only) ................... 386 14 ® Intel ICH8 Family Datasheet ...
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... ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................. 412 9.8.3.18 GPE_CNTL— General Purpose Control Register............................ 412 9.8.3.19 DEVACT_STS — Device Activity Status Register .......................... 413 9.8.3.20 SS_CNT— Intel SpeedStep Control Register (Mobile Only) .................................................. 414 9.8.3.21 C3_RES— C3 Residency Register (Mobile Only) ........................... 414 9.8.3.22 C5_RES— ...
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... DID—Device Identification Register (IDE—D31:F1).................................... 448 11.1.3 PCICMD—PCI Command Register (IDE—D31:F1) ...................................... 449 11.1.4 PCISTS — PCI Status Register (IDE—D31:F1)........................................... 450 11.1.5 RID—Revision Identification Register (IDE—D31:F1).................................. 451 11.1.6 PI—Programming Interface Register (IDE—D31:F1) .................................. 451 16 ® Intel ICH8 Family Datasheet ...
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... When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ...................................................... 469 12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ...................................................... 470 12.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 470 12.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2) ................................................................ 470 ® Intel ICH8 Family Datasheet 17 ...
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... Indexed Register Data Register ............................................ 490 12.1.39STTT1—SATA Indexed Registers Index 00h (SATA TX Termination Test Register 1) .................................................... 492 12.1.40SIR18—SATA Indexed Registers Index 18h (SATA Initialization Register 18h) ........................................................... 492 12.1.41STME—SATA Indexed Registers Index 1Ch (SATA Test Mode Enable Register) .......................................................... 492 18 ® Intel ICH8 Family Datasheet ...
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... Serial ATA Index/Data Pair Superset Registers .................................................... 510 12.3.1 SINDX—SATA Index Register (D31:F5) ................................................... 510 12.3.2 SDATA—SATA Index Data Register (D31:F5)............................................ 511 12.4 AHCI Registers (D31:F2) (Intel ICH8M-E Only)................................................................................................ 512 12.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................... 513 12.4.1.1 CAP—Host Capabilities Register (D31:F2)................................... 513 12.4.1.2 GHC— ...
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... Identification Register (SATA–D31:F5) .................................................................................... 546 13.1.18CAP—Capabilities Pointer Register (SATA–D31:F5) .................................... 546 13.1.19INT_LN—Interrupt Line Register (SATA–D31:F5)....................................... 547 13.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5) ........................................ 547 13.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5) ....................................... 547 20 ® Intel ICH8 Family Datasheet ...
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... MLT—Master Latency Timer Register (USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 569 14.1.10HEADTYP—Header Type Register (USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 570 14.1.11BASE—Base Address Register (USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 570 14.1.12SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 570 ® Intel ICH8 Family Datasheet 21 ...
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... EHCI Subsystem ID Register (USB EHCI—D29:F7, D26:F7)................................................................. 591 15.1.13CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7, D26:F7)................................................................. 591 15.1.14INT_LN—Interrupt Line Register (USB EHCI—D29:F7, D26:F7)................................................................. 591 15.1.15INT_PN—Interrupt Pin Register (USB EHCI—D29:F7, D26:F7)................................................................. 591 22 ® Intel ICH8 Family Datasheet ...
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... Capability Register (USB EHCI—D29:F7, D26:F7) ..................................... 597 15.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7, D26:F7) ............................. 598 15.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7, D26:F7) ................................................................ 600 15.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7, D26:F7) ................................................................ 601 15.1.30EHCIIR1— ...
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... Intel High Definition Audio Controller Registers (D27:F0).................................... 643 ® 17.1 Intel High Definition Audio PCI Configuration Space (Intel Definition Audio— D27:F0)................................................................................ 643 17.1.1 VID—Vendor Identification Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 645 24 ® ...
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... High Definition Audio Controller—D27:F0)..................................... 648 17.1.11HEADTYP—Header Type Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 649 17.1.12HDBARL—Intel Register (Intel 17.1.13HDBARU—Intel Register (Intel 17.1.14SVID—Subsystem Vendor Identification Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 650 17.1.15SID—Subsystem Identification Register ® ...
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... High Definition Audio Controller—D27:F0) ..................................... 663 17.1.46VCiSTS—VCi Resource Status Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 663 17.1.47RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel Controller—D27:F0) .............................................................................. 664 17.1.48ESD—Element Self Description Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 664 17.1.49L1DESC— ...
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... Write Pointer Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 683 17.2.27RINTCNT—Response Interrupt Count Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 684 17.2.28RIRBCTL—RIRB Control Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 684 17.2.29RIRBSTS—RIRB Status Register ® ...
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... High Definition Audio Controller—D27:F0) ..................................... 694 17.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel Controller—D27:F0) .............................................................................. 695 17.2.45SDBDPU—Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel Controller—D27:F0) .............................................................................. 695 18 PCI Express* Configuration Registers .................................................................... 697 18.1 PCI Express* Configuration Registers (PCI Express— ...
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... Vendor Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 722 18.1.41SVID—Subsystem Vendor Identification Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 722 18.1.42PMCAP—Power Management Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 722 18.1.43PMC—PCI Power Management Capabilities Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 723 ® Intel ICH8 Family Datasheet 29 ...
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... GEN_CONF—General Configuration Register ............................................. 743 19.1.3 GINTR_STA—General Interrupt Status Register......................................... 743 19.1.4 MAIN_CNT—Main Counter Value Register ................................................. 744 19.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register ..................... 744 19.1.6 TIMn_COMP—Timer n Comparator Value Register ..................................... 746 30 ® PRO/Wireless 3945ABG Status ® Intel ICH8 Family Datasheet ...
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... Memory Mapped Configuration Registers) ......................................... 761 20.1.24VSCC—Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) ......................................... 762 20.2 Flash Descriptor Registers ................................................................................ 763 20.2.1 Flash Descriptor Content ....................................................................... 763 20.2.1.1 FLVALSIG—Flash Valid Signature Register (Flash Descriptor Memory Mapped Configuration Registers) .............................................................................. 763 ® Intel ICH8 Family Datasheet 31 ...
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... FADDR—Flash Address Register (GbE LAN Memory Mapped Configuration Registers) .................................. 780 20.3.5 FDATA0—Flash Data 0 Register (GbE LAN Memory Mapped Configuration Registers) .................................. 780 20.3.6 FRAP—Flash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) .................................. 781 32 ® Intel ICH8 Family Datasheet ...
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... TSxE—Thermal Sensor [1:0] Enable ....................................................... 798 21.2.2 TSxS—Thermal Sensor[1:0] Status......................................................... 798 21.2.3 TSxTTP—Thermal Sensor [1:0] Catastrophic Trip Point .............................. 798 21.2.4 TSxCO—Thermal Sensor [1:0] Catastrophic Lock-Down............................. 799 21.2.5 TSxPC—Thermal Sensor [1:0] Policy Control ............................................ 799 ® Intel ICH8 Family Datasheet 33 ...
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... Thermal Specifications...................................................................................... 819 23.2 Absolute Maximum Ratings4 ............................................................................. 819 23.3 DC Characteristics ........................................................................................... 820 23.4 AC Characteristics............................................................................................ 832 23.5 Timing Diagrams ............................................................................................. 851 24 Package Information ............................................................................................. 867 24.1 Package Dimensions (Desktop Only)................................................................... 867 24.2 Package Dimensions (Mobile Only) ..................................................................... 869 A Register Bit Index .................................................................................................. 872 34 ® Intel ICH8 Family Datasheet ...
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... ICH8 DMA Controller ..................................................................................... 129 9 DMA Request Assertion through LDRQ# .................................................................... 132 10 Coprocessor Error Timing Diagram ........................................................................... 157 11 Advanced TCO Intel® AMT Mode SMBus/SMLink Configuration ..................................... 187 12 Advanced TCO BMC Mode SMBus/SMLink Configuration............................................... 188 13 Physical Region Descriptor Table Entry...................................................................... 191 14 SATA Power States................................................................................................. 200 15 USB Legacy Keyboard Flow Diagram ...
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... Power Plane and States for Output and I/O Signals for Mobile Configurations....................98 35 Power Plane for Input Signals for Desktop Configurations............................................. 102 36 Power Plane for Input Signals for Mobile Configurations ............................................... 104 ® 37 Intel ICH8 and System Clock Domains .................................................................... 107 38 PCI Bridge Initiator Cycle Types ............................................................................... 109 39 Type 1 Address Format ........................................................................................... 112 40 MSI vs ...
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... Configuration Bits Reset by RTCRST# Assertion ......................................................... 154 59 INIT# Going Active ................................................................................................ 156 60 NMI Sources.......................................................................................................... 157 61 DP Signal Differences ............................................................................................. 158 62 General Power States for Systems Using Intel 63 State Transition Rules for Intel 64 System Power Plane ............................................................................................... 162 65 Causes of SMI# and SCI ......................................................................................... 163 66 Break Events (Mobile Only) ..................................................................................... 166 67 Sleep Types ...
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... Fixed I/O Ranges Decoded by Intel 101 Variable I/O Decode Ranges..................................................................................... 260 102 Memory Decode Ranges from Processor Perspective.................................................... 261 103 Chipset Configuration Register Memory Map (Memory Space) ....................................... 265 104 Gigabit LAN Configuration Registers Address Map (Gigabit LAN —D25:F0) ........................................................................................... 309 105 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) .......................................... 323 106 DMA Registers ....................................................................................................... 344 107 PIC Registers (LPC I/F— ...
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... SATA Interface Timings........................................................................................... 842 164 SMBus Timing........................................................................................................ 842 166 LPC Timing............................................................................................................ 843 167 Miscellaneous Timings ............................................................................................ 843 ® 165 Intel High Definition Audio Timing .......................................................................... 843 168 SPI Timings (20 MHz) ............................................................................................. 844 169 SPI Timings (33 MHz) ............................................................................................. 844 170 SST Timings (Desktop Only) ................................................................................... 845 171 PECI Timings (Desktop Only) ...
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... Added 82801HDH ICH8 Digital Home (ICH8DH) and 82801HDO ICH8 Digital Office -002 (ICH8DO) ® • Added Intel 82801HBM ICH8 Mobile (ICH8M) and Intel Enhanced (ICH8M-E) -003 • Added Documentation Changes, Specification Changes, and Specification Clarifications from Specification Update, Rev -008. ...
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... Allows for non-48 kHz sampling output — Support for ACPI Device States — Low Voltage Mode — Docking Support (Mobile only) ® NEW: Intel Quiet System Technology (Desktop Only) — Four TACH signals and three PWM signals NEW: Simple Serial Transport (SST) ...
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... Supports ACPI 3.0 — ACPI-defined power states (C1, S1, S3–S5 for Desktop and C1–C4, S1, S3–S5 for Mobile) — ACPI Power Management Timer — (Mobile Only) Support for “Intel SpeedStep power control and “Deeper Sleep” power state — PCI CLKRUN# (Mobile only) and PME# support — ...
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... In te l® fin itio l® ® Intel ICH8 Family Datasheet DMI (To (G)MCH) USB 2.0 (Supports 10 USB ports Dual EHCI Controller) SATA (6 ports) ® Intel ICH8 Intel® High Definition Audio Codec(s) PCI Express* x1 GLCI LCI GPIO LPC I/F Other ASICs (Optional) TPM (Optional ® ...
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... Intel ICH8 Family Datasheet ...
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... PCI Local Bus Specification, Revision 2.3 (PCI) PCI Mobile Design Guide, Revision 1.1 PCI Power Management Specification, Revision 1.1 ® Intel ICH8 Family Datasheet ® ® High Definition Audio (Intel HD Audio), SMBus, PCI, ACPI and Table 1 Specification for the complete details. Location http://www.intel.com/design/ chipsets/specupdt/313057.htm http://www ...
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... ICH8 and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. Intel Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset ...
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... SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 16. Intel Chapter 17 provides a detailed description of all registers that reside in the Intel High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 17. PCI Express* Port Controller Registers Chapter 18 provides a detailed description of all registers that reside in the PCI Express controller ...
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... PCI-to-ISA bridges (South Bridges). The third and fourth devices (Device 29 and Device 26) are the USB host controller devices. The fifth device (Device 28) is PCI Express device. The sixth device (Device 27) is the Intel HD Audio controller device, and the seventh device (Device 25) is the GbE controller device ...
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... USB FS/LS UHCI Controller 3 USB HS EHCI Controller 1 USB FS/LS UHCI Controller 4 USB FS/LS UHCI Controller 5 USB HS EHCI Controller 2 PCI Express* Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 PCI Express Port 5 PCI Express Port 6 ® Intel High Definition Audio Controller GbE Controller 49 ...
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... Intel Matrix Storage Technology (Intel Only) ICH8M-E The ICH8 provides support for Intel Matrix Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID and 10 functionality SATA ports of ICH8. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks ...
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... The ICH8 implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH, and is required to support Intel Active Management Technology (ICH8DO and ICH8M-E only) and the integrated Fan Speed Control (Intel ICH8 supports up to two SPI flash devices with speeds MHz using two chip select pins ...
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... GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH8 configuration. 52 Introduction Section 5.18 and Section 5.19 Section 5.3 for details. ® Intel ICH8 Family Datasheet ...
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... Quick Resume Technology (QRT) (Intel ICH8DH implements Intel Quick Resume Technology (QRT) to give the PC a Consumer Electronics device-like feel. Intel QRT provides the capability to design a PC with a single power button that reliably and instantly (user's perception) turns the PC On and Off. When the system is On and the user presses the power button, the display instantly goes dark, sound is muted, and there is no response to keyboard/mouse commands (except for keyboard power button) ...
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... High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH8 Intel HD Audio controller supports codecs. The link can operate at either 3 1.5 V. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE levels of audio experience ...
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... ICH8 Family Datasheet Short Name SATA Ports (#) ICH8 4 ICH8R 6 ICH8DH 6 ICH8DO 6 Intel Short SATA Ports Storage Technology Name (#) RAID 0/1 Support ICH8M 3 ICH8M-E 3 § § ® Intel Matrix Storage Technology No Yes Yes Yes ® ® Matrix Intel Active Management Technology No No Yes Yes 55 ...
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... Introduction ® Intel ICH8 Family Datasheet ...
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... The following notations are used to describe the signal type I/OD I/O OC ® Intel ICH8 Family Datasheet Input Pin Output Pin Open Drain Output Pin. Bi-directional Input/Open Drain Output Pin. Bi-directional Input / Output Pin. Open Collector Output Pin. 57 ...
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... HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN[3:0] DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH4 / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH4 LDRQ0# LDRQ1# / GPIO23 SMBDATA SMBCLK SMBALERT# / GPIO11 INTRUDER# SMLINK[1:0] LINKALERT# CLGPIO0/GPIO24;CLGPIO1/GPIO10 CLGPIO2/GPIO14;WOL_EN/GPIO9 GLAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC QRT_STATE[1:0] / GPIO[28:27] ® Intel ICH8 Family Datasheet ...
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... SMBus Interface General System Purpose Mgnt. I/O DCS1# DCS3# Platform DA[2:0] LAN IDE Connect DDREQ Interface Intel Quick Resume Technology GLAN_CLK GLAN_TXp/PET6p; GLAN_TXn/PET6n GLAN_RXp/PER6p; GLAN_RXn/PER6n GLAN_COMPO GLAN_COMPI GLAN_DOCK#/GPIO13 CL_CLK[1:0] ; CL_DATA[1:0] CL_VREF[1:0] CL_RST# PETp[5:1], PETn[5:1] PERp[5:1], PERn[5:1] GLAN_TXp/PET6p; GLAN_TXn/PET6n GLAN_RXp/PER6p; GLAN_RXn/PER6n ...
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... PCI Express Differential Transmit Pair 6: The differential O pair functions as the GbE LAN transmit pair when the integrated GbE controller is enabled. PCI Express Differential Receive Pair 6: The differential pair I functions as the GbE LAN receive pair when the integrated GbE controller is enabled. Signal Description ® Intel ICH8 Family Datasheet ...
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... GLAN_RXp/PER6p; GLAN_RXn/PER6n GLAN_COMPO GLAN_COMPI GLAN_DOCK# (Mobile Only)/ GPIO12 ® Intel ICH8 Family Datasheet Type Description GbE Input Clock: This clock is driven by LAN Connect Device. The frequency will vary depending on link speed. I NOTE: The clock is shared between LAN Connect Interface and Gigabit LAN Connect Interface. ...
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... LAN Connected Device must be restored. This signal connects to the output of an external link detect circuit and I is required to implement the Intel feature for LAN Connect Device Full Power Down savings. This signal may instead be used as a GPIO. LAN Reset/Sync: This is the reset/sync signal from the GbE LAN interface to the physical device. The LAN Connect component’ ...
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... During the first clock of a transaction, AD[31:0] contain a I/O physical address (32 bits). During subsequent clocks, AD[31:0] ® contain data. The Intel ICH8 will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins ...
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... The ICH8 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The ICH8 supports masters on the PCI bus. I REQ[3:1]# pins can instead be used as GPIO. Signal Description ® Intel ICH8 Family Datasheet ...
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... GNT2#/ GPIO53 GNT3#/GPIO55 PCICLK PCIRST# PLOCK# SERR# PME# ® Intel ICH8 Family Datasheet Type Description PCI Grants: The ICH8 supports masters on the PCI bus. GNT[3:1]# pins can instead be used as GPIO. Pull-up resistors are not required on these signals. If pull-ups are O used, they should be tied to the Vcc3_3 power rail. ...
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... Controller 1. NOTE: This port is not functional in the Desktop ICH8 Base component. Serial ATA 4 Differential Transmit Pair: These are outbound high-speed differential signals to Port compatible mode, SATA Port 4 is the primary master of SATA Controller 2 Signal Description Description ® Intel ICH8 Family Datasheet ...
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... SATA3GP (Desktop Only) / GPIO37 SATA4GP (Desktop Only) SATA5GP (Desktop Only) ® Intel ICH8 Family Datasheet Type Serial ATA 4 Differential Receive Pair: These are inbound high- speed differential signals from Port compatible mode, SATA Port 4 is the primary master of SATA Controller 2 Serial ATA 5 Differential Transmit Pair: These are outbound high-speed differential signals to Port 5 ...
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... DRQ signal on the IDE connector asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on this signal. Signal Description Description ® Intel ICH8 Family Datasheet ...
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... ICH8 Family Datasheet Description IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel ...
Page 70
... PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. IDE Interrupt Request: This interrupt input is connected to the IDE I drive. Signal Description ® Intel ICH8 Family Datasheet ...
Page 71
... These ports can be routed to UHCI controller #1 or the EHCI controller #1. I/O NOTE: No external resistors are required on these signals. The ® Intel ICH8 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3 ...
Page 72
... Used to set transmit currents and internal load resistors. Description ® Platform Reset: The Intel ICH8 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH8 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h) ...
Page 73
... ICH8’s DRAM power-cycling feature. Refer to Chapter 5.13.11.2 for details O NOTE system with Intel AMT support, this signal should be used to control the DRAM power state (where the host platform is in S3-S5 states and the manageability sub-system is running) the signal is forced high along with SLP_M# in order to properly maintain power to the DIMM used for manageability sub-system ...
Page 74
... It does not need to meet any particular setup or hold time. NOTE: In desktop configurations, this signal is a GPIO. PCI Clock Run: This signal is used to support PCI CLKRUN protocol. It connects to peripherals that need to request clock restart or prevention of clock stopping. Signal Description ® Intel ICH8 Family Datasheet ...
Page 75
... CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during O that time, no snoops occur. The Intel CPUSLP# signal when going to the S1 state. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH8 coprocessor error reporting function is enabled in the OIC ...
Page 76
... Deeper Sleep: DPSLP# is asserted by the ICH8 to the processor. When the signal is low, the processor enters the deep sleep state by O gating off the processor Core Clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state. Signal Description ® Intel ICH8 Family Datasheet ...
Page 77
... CL_RST1# CLGPIO0 (MEM_LED)/ GPIO24 SusPwrAck/ ALERT# (Mobile Only)/ GPIO10 ® Intel ICH8 Family Datasheet Type I/OD SMBus Data: External pull-up resistor is required. I/OD SMBus Clock: External pull-up resistor is required. SMBus Alert: This signal is used to wake the system or generate I SMI#. If not used for SMBALERT#, it can be used as a GPIO. ...
Page 78
... To support WOL out state, the WOL_EN pin needs to be pulled high by an external resistor until the Manageability Engine is initialized. If Intel AMT or integrated ASF are disabled on a board that is configured for WOL_EN support, BIOS must use GPIO9 to control power to the LAN subsystem when entering S3–S5. ...
Page 79
... RTCRST# TP0 (Desktop Only) / BATLOW# (Mobile Only) ® Intel ICH8 Family Datasheet Description Oscillator Clock: This clock is used for 8254 timers. It runs at 14.31818 MHz. This clock is permitted to stop during S3 (or lower) states. 48 MHz Clock: This clock is used to run the USB controller. It runs at 48 ...
Page 80
... Intel High Definition Audio Reset: This signal is a master O hardware reset to external codec(s). Intel High Definition Audio Sync: This signal kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. O NOTE: HDA_SYNC is sampled at the rising edge of PWROK as a functional strap ...
Page 81
... ICH8 Family Datasheet Type Intel High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio. O NOTE: HDA_SDOUT is sampled at the rising edge of PWROK as a functional strap ...
Page 82
... Intel Quick Resume Technology State: Intel Quick Resume Technology status signals that may optionally be used to drive front chassis indicators. See I/O When Intel Quick Resume Technology is enabled, the signals will function as QRT_STATE[1:0] only. Otherwise, the signals are used as GPIOs. Type Description ...
Page 83
... ICH8 Family Datasheet Type Description Fan Pulse Width Modulation Outputs: This is a Pulse Width Modulated duty cycle output signal that is used Intel Quiet System Technology. When controlling a 3-wire fan, this signal controls a power OD transistor that, in turn, controls power to the fan. When controlling a 4-wire fan, this signal is connected to the “ ...
Page 84
... STP_CPU# Desktop: Default as STP_CPU# (Note 3) Mobile: Multiplexed with MEM_LED Desktop: Multiplexed with CLGPIO0. Not cleared by CF9h reset event. Multiplexed with LDRQ1# (Note 5) Multiplexed with SCLOCK Multiplexed with SATA0GP. Unmultiplexed Multiplexed with SATA1GP Unmultiplexed Multiplexed with TACH0 ® Intel ICH8 Family Datasheet ...
Page 85
... If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low Power Button Override event will result in the Intel ICH8 driving a pin to a logic 1 to another device that is powered down. 3. The functionality that is multiplexed with the GPIO may not be used in desktop configuration ...
Page 86
... V power supply when the integrated VRM is disabled. This pin can be left the internal VRM is used unless decoupling is required. 86 Description Section 2.26.1 Section 2.26.1 for strapping option). This pin must be connected to an external Signal Description for strapping option). for strapping option). ® Intel ICH8 Family Datasheet ...
Page 87
... VccSusHDA desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. Core supply for Intel High Definition Audio. This pin can be either 1.5 or 3.3 V. VccHDA This power may be shut off in S3, S4 states. 3.3 V (can drop to 2.0 V min state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained ...
Page 88
... BIOS space). The status of this strap is readable PWROK via the Top Swap bit (Chipset Configuration Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Signal Description for information on Comment ® Intel ICH8 Family Datasheet ...
Page 89
... LAN_RST# pin, whichever rises first. Note that the hold time is also required to meet the minimum of 101 ms after the RSMRST# pin is deasserted in the case both ICH8 ME well and AUX well are connected to the Resume Well power. ® Intel ICH8 Family Datasheet When Sampled This field determines the destination of accesses to the BIOS memory range ...
Page 90
... KΩ + Vbatt – NOTE: C1 and C2 depend on crystal load. 90 Schottky 1 µF Diodes (20% tolerance) 20 KΩ 32.768 kHz Xtal 1 µF C1 (20% tolerance (5% tolerance) § § Signal Description Figure 3 shows an example VCCRTC RTCX2 R1 10 MΩ RTCX1 (5% tolerance) RTCRST# ® Intel ICH8 Family Datasheet ...
Page 91
... The pull-down on this signal is only enabled when in S3. 10. Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ. 11. The integrated resistors are disabled after PLTRST# de-assertion. ® Intel ICH8 Family Datasheet ICH8 Pin States Resistor Ty Pull-down Pull-down ...
Page 92
... Clock is toggling or signal is transitioning because function not stopping. The power plane is off; ICH8 is not driving when configured as an output or sampling when configured as an input. ICH8 is sampling and signal state determined by external driver. ® Intel ICH8 Pin States ® Intel ICH8 Family Datasheet ...
Page 93
... IRDY#, TRDY# PAR PCIRST# Suspend PERR# PLOCK# STOP# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LAN_RSTSYNC LAN_TXD[2:0] GLAN_TXp, GLAN_TXn SATA[5:0]TXP, SATA[5:0]TXN SATALED# SATARBIAS ® Intel ICH8 Family Datasheet During Immediately 4 Plane Reset after Reset PCI Express* 8 Core High High DMI 8 Core High High PCI Bus ...
Page 94
... Input Interrupts Core High-Z High-Z Core High-Z High-Z ® Intel ICH8 Pin States S1 S3 S4/S5 4 Driven Off Off Defined Off Off Defined Off Off Defined Off Off Defined Off Off High-Z Off Off High-Z Off Off ® Intel ICH8 Family Datasheet ...
Page 95
... IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# SMBCLK, SMBDATA Suspend CLGPIO0 Suspend WOL_EN Suspend SMLINK[1:0] Suspend LINKALERT# Suspend ® Intel ICH8 Family Datasheet During Immediately 4 Plane Reset after Reset USB Interface Low Low High-Z High-Z Power Management Low High Low High ...
Page 96
... GPIO14 Suspend GPIO15 Suspend GPIO16 GPIO18 GPIO20 GPIO25 GPIO[33:32] GPIO34 Controller SPI_CS[1:0]# Controller SPI_MOSI Controller SPI_CLK ® Intel Quick Resume Technology Interface (Intel QRT_STATE[1:0] / Suspend GPIO[28:27] 96 During Immediately 4 Plane Reset after Reset Miscellaneous Signals High-Z with Core Internal Low Pull-down ® ...
Page 97
... ICH8 drives these signals Low before PWROK rising and Low after the processor Reset. 6. SLP_S5# signals will be high in the S4 state. 7. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 8. ...
Page 98
... High-Z Off Off High Off Off High Off Off Defined Off Off Defined Off Off Defined Off Off Undefined Off Off High Off Off High-Z Off Off Low Off Off High Off Off High Off Off ® Intel ICH8 Family Datasheet ...
Page 99
... SUS_STAT# Suspend DPRSLPVR Core DPRSTP# Core SUSCLK Suspend CK_PWRGD Suspend A20M# CPU CPUPWRGD / GPIO49 CPU IGNNE# CPU INIT# CPU ® Intel ICH8 Family Datasheet During Immediately C3/ Reset after Reset SATA Interface High-Z High-Z Defined High-Z High-Z Defined High-Z High-Z Defined Input ...
Page 100
... Defined Defined Defined Defined Defined Defined Off Off High TBD Low Low Low Off Off Low Off Off Low Off Off Defined Off Off Defined Off Off Driven Driven Driven Driven Off Off Defined Off Off ® Intel ICH8 Family Datasheet ...
Page 101
... ICH8 drives these signals Low before PWROK rising and Low after the processor Reset. 6. SLP_S5# signals will be high in the S4 state. 7. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 8. ...
Page 102
... Running Off Off Driven Driven Driven High Off Off High Off Off High Off Off Driven Driven Driven Driven Driven Driven Driven Driven Driven Running Off Off Driven Off Off Driven Off Off Driven Off Off ® Intel ICH8 Family Datasheet ...
Page 103
... Miscellaneous Signals RTC External Pull-up RTC External Pull-up RTC External RC Circuit Suspend External Pull-up Suspend Internal Pull-up ® Intel High Definition Audio Interface Intel® High Definition Suspend Audio Codec S1 S3 S4/S5 Driven Driven Driven Driven Driven Driven Driven Driven Driven ...
Page 104
... Driven Driven Off Off Driven Driven Off Off Running Running Off Off Driven Driven Driven Driven Driven Driven Off Off Driven High Off Off Driven High Off Off Driven High Off Off Driven Driven Driven Driven ® Intel ICH8 Family Datasheet ...
Page 105
... PWROK RI# Suspend RSMRST# Suspend SYS_RESET# Suspend THRM# THRMTRIP# VRMPWRGD Suspend WAKE# Suspend ® Intel ICH8 Family Datasheet Power Driver During Reset Well LAN Connect Component Gigabit LAN Connect Interface Gigabit Lan Connect Component SATA Interface Core Clock Generator Core SATA Drive ...
Page 106
... High High High High High High High High High Driven High High High High High High High High High High Driven Low Low Low Driven Driven Driven Driven Running Running Off Off Running Running Off Off ® Intel ICH8 Family Datasheet ...
Page 107
... Differential clock pair used for SATA. Generator Main Clock 100 MHz Differential clock pair used for DMI. Generator Free-running PCI Clock to Intel clock remains on during S0 and S1 (in desktop) Main Clock 33 MHz state, and is expected to be shut off during S3 Generator or below in desktop configurations below in mobile configurations ...
Page 108
... PCI Clocks (33 MHz) Gen. 14.31818 MHz 48.000 MHz PCI Express Differential 100 MHz Clock Fan Diff. Pairs Out Device PCI Clocks (33 MHz) 14.31818 MHz 48 MHz PCI Express Differential 100 MHz Clock Fan Diff. Pairs Out Device ® Intel ICH8 Family Datasheet ...
Page 109
... The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the following cycle types: Table 38. PCI Bridge Initiator Cycle Types Command I/O Read/Write Memory Read/Write Configuration Read/Write Special Cycles ® Intel ICH8 Family Datasheet C/BE# Notes 2h/3h Non-posted 6h/7h Writes are posted Ah/Bh Non-posted ...
Page 110
... FRAME# at the next valid clock edge when there is another active request to use the PCI bus. 5.1.2.6 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 110 Functional Description ® Intel ICH8 Family Datasheet ...
Page 111
... The PCIRST# pin is generated under two conditions: • PLTRST# active • BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but not other agents in the system. ® Intel ICH8 Family Datasheet 111 ...
Page 112
... ICH8 asserts AD31. Note that the ICH8’s internal functions (Intel High Definition Audio, IDE (Mobile only), USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. ...
Page 113
... One or more bits set to 1, software clears some (but not all) bits One or more bits set to 1, software clears all bits Software clears one or more bits, and one or more bits are set on the same clock ® Intel ICH8 Family Datasheet Interrupt Register Wire-Mode MSI Action Action ...
Page 114
... RCTL.PIE is later written from and interrupt must be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 114 Functional Description HOT Section 5.2.2.4 for SMI/SCI generation. ® Intel . When a device ICH8 Family Datasheet ...
Page 115
... F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt. ® Intel ICH8 Family Datasheet PCICMD.SEE Correctable SERR# Fatal SERR# Non-Fatal SERR# PSTS ...
Page 116
... SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/ F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated. 116 Functional Description ® Intel ICH8 Family Datasheet ...
Page 117
... Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 4) When any of these bits are set, SMI # will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. ® Intel ICH8 Family Datasheet 117 ...
Page 118
... Gigabit Ethernet Controller (B0:D25:F0) The ICH8 integrates a Gigabit Ethernet Controller. The integrated GbE controller is compatible with Intel 10/100 PHY (Intel® 82562V Platform LAN Connect device) and ® GbE PHY (Intel 82566 Gigabit Platform LAN Connect device). The integrated GbE controller provides two interfaces: LCI for 10/100 operation and GLCI for GbE operation. The GLCI is shared with the ICH8’ ...
Page 119
... LAN connect interface (LCI) or GbE LAN connect interface (GLCI). All controller configuration is performed using device control registers mapped into system memory or I/O space. The LAN Connect Device is configured via the LCI or GbE Lan connect interface. The integrated MAC supports various modes as summarized in ® Intel ICH8 Family Datasheet Table 41. 119 ...
Page 120
... Control Word into the APM Enable (APME) bits of the Wakeup Control Register (WUC). These bits control enabling of APM Wakeup. When APM Wakeup is enabled, the LAN Controller checks all incoming packets for "Magic Packets". 120 Interface Active LCI LCI, GLCI Intel Functional Description Connections 82562 82566 ® ICH8 Family Datasheet ...
Page 121
... Wake Up Status Register (WUS). It will also ignore link change events until the driver clears the Link Status Changed (LNKC) bit in the Wake Up Status Register (WUS). ® Intel ICH8 Family Datasheet 121 ...
Page 122
... The Intel ACBS feature is controlled by the LAN Driver. The SW driver is responsible for the PLC transitioning into Intel ACBS mode and the ICH8M Gigabit LAN Controller HW is responsible for detecting the presence of a link partner which indicates that the Intel ACBS mode should be terminated. ...
Page 123
... Application Note (AP-496) for details. The LAN PHY power control feature is required to fully power down the PLC device. This feature is also used to restore power to the PLC device when the ENERGY_DETECT signal is asserted and the PLC device is in Intel ACBS mode. A platform designer may choose to implement Intel ACBS without the LAN PHY Power Control feature ...
Page 124
... The ICH8 implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the ICH8 is shown in that the ICH8 implements all of the signals that are shown as optional, but peripherals are not required to do so. Figure 7. LPC Interface Diagram 124 Functional Description Figure 7. Note ® Intel ICH8 Family Datasheet ...
Page 125
... ICH8 Family Datasheet Table 42 shows the cycle types supported by the ICH8. Comment ® 1 byte only. Intel ICH8 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. 1 byte only. ICH8 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. Can bytes Can bytes Can bytes ...
Page 126
... Bits[1:0] are encoded as listed in Table 45. Transfer Size Bit Definition Bits[1:0] 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) Reserved. The Intel 10 a bus master cycle drives this combination, the ICH8 may abort the transfer. 11 32-bit transfer (4 bytes) 126 Table 44 shows the valid bit encodings. ...
Page 127
... Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA 0000 request deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel 0101 does not use this encoding. Instead, the ICH8 uses the Long Wait encoding (see next encoding below) ...
Page 128
... CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. 5.4.1.12 Configuration and Intel LPC I/F Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH8 includes several decoders. During configuration, the ICH8 must be programmed with the same decode ranges as the peripheral ...
Page 129
... DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in ® Intel ICH8 Family Datasheet (Figure 8). DMA controller 1 (DMA-1) Channel 4 ...
Page 130
... Similarly 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. 130 Functional Description ® Intel ICH8 Family Datasheet ...
Page 131
... DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. ® Intel ICH8 Family Datasheet Current Byte/Word Count Register Bytes ...
Page 132
... I/O device to request use of the LPC interface, and the I/O device does not need to self- arbitrate before sending the message. Figure 9. DMA Request Assertion through LDRQ# LCLK LDRQ# 132 Figure Start MSB LSB Functional Description 9, the peripheral uses ACT Start ® Intel ICH8 Family Datasheet ...
Page 133
... On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred. ® Intel ICH8 Family Datasheet 133 ...
Page 134
... The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237’s address and decrementing its byte count. 134 Functional Description ® Intel ICH8 Family Datasheet ...
Page 135
... This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports). ® Intel ICH8 Family Datasheet 135 ...
Page 136
... Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 49 lists the six operating modes for the interval counters. 136 Functional Description ® Intel ICH8 Family Datasheet ...
Page 137
... Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. ® Intel ICH8 Family Datasheet Function Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. ...
Page 138
... The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 138 Functional Description ® Intel ICH8 Family Datasheet ...
Page 139
... Therefore, the term “high” indicates “active,” which means “low” originating PIRQ#. ® Intel ICH8 Family Datasheet Typical Interrupt Connected Pin / Function Source ...
Page 140
... Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 140 Table 51 defines the IRR, ISR, and IMR. Description Bits [7:3] Bits [2:0] 111 110 101 100 ICW2[7:3] 011 010 001 000 Functional Description ® Intel ICH8 Family Datasheet ...
Page 141
... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. ® Intel ICH8 Family Datasheet 141 ...
Page 142
... ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.8.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • ...
Page 143
... In this mode, internal status is updated by software control during OCW2. However independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO–L2=IRQ level to receive bottom priority. ® Intel ICH8 Family Datasheet 143 ...
Page 144
... PIC within the ICH8, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can determine which ISR bit to clear 144 Functional Description ® Intel ICH8 Family Datasheet ...
Page 145
... PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH8 receives the PIRQ input, like all of the other external sources, and routes it accordingly. ® Intel ICH8 Family Datasheet 145 ...
Page 146
... Option for SCI, TCO No Yes Option for SCI, TCO No Yes HPET #2, Option for SCI, TCO No Yes No No FERR# logic Mobile Only: IDEIRQ (legacy mode, non- 1 Yes Yes combined or combined mapped as primary), SATA Primary (legacy mode) Functional Description Internal Modules ® Intel ICH8 Family Datasheet ...
Page 147
... The address and data formats are described below in Section Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH8. ® Intel ICH8 Family Datasheet Direct Via PCI from Pin Message Mobile Only: IDEIRQ (legacy mode — combined, ...
Page 148
... Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical 2 destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00. 148 Functional Description Table 54 and Table 55 for the address and Description ® Intel ICH8 Family Datasheet ...
Page 149
... The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH8 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. ® Intel ICH8 Family Datasheet Description 149 ...
Page 150
... IRQ8#. RTC interrupt can only be generated internally. • IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. 150 Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (Intel Frame Functional Description ® ICH8) may initiate a Start ® ...
Page 151
... IRQ13 15 IRQ14 16 IRQ15 17 IOCHCK# 18 PCI INTA# 19 PCI INTB# 20 PCI INTC# 21 PCI INTD# ® Intel ICH8 Family Datasheet Clocks Past Start Frame Ignored. IRQ0 can only be generated via the internal 2 8524 5 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit Ignored. IRQ8# can only be generated internally. ...
Page 152
... To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 152 Functional Description ® Intel ICH8 Family Datasheet ...
Page 153
... RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. ® Intel ICH8 Family Datasheet Table 58 shows which bits are set to their default state when ...
Page 154
... Power Management 1 PMBase + 04h Control (PM1_CNT) General Purpose Event 0 Enables PMBase + 2Ch Register (GPE0_EN) General Purpose Event 0 Enables PMBase + 2Ch Register (GPE0_EN) General Purpose Event 0 Enables PMBase + 2Ch Register (GPE0_EN) Functional Description Default Bit(s) State 7 12: ® Intel ICH8 Family Datasheet ...
Page 155
... The ICH8 interfaces to the processor with a variety of signals • Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP#, CPUPWRGD • Standard Input from processor: FERR# • Intel SpeedStep configurations) Most ICH8 outputs to the processor use standard buffers. The ICH8 has separate V ...
Page 156
... Functional Description Comment INIT# assertion based on value of Shutdown Policy Select register (SPS transition on RCIN# must occur ® before the Intel ICH8 will arm INIT generated again. NOTE: RCIN# signal is expected to be low during S3, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to ...
Page 157
... CPU Power Good (CPUPWRGOOD) This signal is connected to the processor’s PWRGOOD input. This signal represents a logical AND of the ICH8’s PWROK and VRMPWRGD signals. ® Intel ICH8 Family Datasheet Comment Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11) ...
Page 158
... ICH8 only supports the C1 state for dual-processor designs. In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by the processors. The Intel ICH8 also has the option to assert the processor’s SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the transition to the S1 state), the processors will not be executing code that is likely to delay the Stop-Grant cycles ...
Page 159
... ACPI G2/S5 state — Soft Off (SOFF) — Power Failure Detection and Recovery • Manageability Engine Power Management Support — New Wake events from the ME (enabled from all S-States including Catastrophic S5 conditions) • Streamlined Legacy Power Management for APM-Based Systems ® Intel ICH8 Family Datasheet 159 ...
Page 160
... Stop-Grant cycle, halts its instruction stream. ICH8 then asserts G0/S0/C3 DPSLP# followed by STP_CPU#, which forces the clock generator to stop the (Mobile processor clock. This is also used for Intel SpeedStep Only) Accesses to memory (by graphics, PCI, or internal units) is not permitted while state. ...
Page 161
... Functional Description Table 63. State Transition Rules for Intel Present State • Processor halt instruction • Level 2 Read (Mobile Only) • Level 3 Read (Mobile Only) Level 4 Read (Mobile Only) G0/S0/C0 • SLP_EN bit set • Power Button Override • Mechanical Off/Power Failure • ...
Page 162
... Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. Section 9.1.3). The interrupt remains asserted until all SCI Functional Description Table 64. Note that Description ® Intel ICH8 Family Datasheet ...
Page 163
... TCO SMI — Message from (G)MCH TCO SMI — NMI occurred (and NMIs mapped to SMI) TCO SMI — INTRUDER# signal goes active TCO SMI — Change of the BIOSWP bit from ® Intel ICH8 Family Datasheet SCI SMI Additional Enables Yes Yes PME_EN=1 Yes ...
Page 164
... BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message ...
Page 165
... A C1 state in desktop or a C1, C2 state in mobile ends due to a Break event. Based on the break event, the ICH8 returns the system to C0 state. (Mobile Only) Table 66 events from C1 are indicated in the processor’s datasheet. ® Intel ICH8 Family Datasheet lists the possible break events from C2, C3, or C4. The break 165 ...
Page 166
... NOT be treated as a break event. Instead, there will be a return only to the C2 state. Only available if FERR# enabled for break event C2, C3, C4 indication (See FERR# Mux Enable in GCS, Chipset Config Registers:Offset 3410h:bit 6) Functional Description ® Intel ICH8 Family Datasheet ...
Page 167
... states. Instead, these will be treated merely as bus master events and return the platform state, and thus allow snoops to be performed. After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even if the ARB_DIS bit is set. ® Intel ICH8 Family Datasheet 167 ...
Page 168
... If an internal device needs the PCI bus, the ICH8 asserts the CLKRUN# signal. 5.13.6.3 Conditions for Stopping the PCI Clock • device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks, the ICH8 stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer. 168 Functional Description ® Intel ICH8 Family Datasheet ...
Page 169
... Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock • Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can occur when system state. ® Intel ICH8 Family Datasheet 169 ...
Page 170
... Event Sets PME_B0_STS bit; PM_B0_EN must be enabled. S1–S5 Can not wake from S5 state if it was entered due to power failure or power button override. S1–S5 PME_B0_EN bit in GPE0_EN register (Note 1) S1–S5 Set PME_EN bit in GPE0_EN register. Functional Description Table 68. How Enabled ® Intel ICH8 Family Datasheet ...
Page 171
... GPI[7:0] GPI[15:8] The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH8 are insignificant. ® Intel ICH8 Family Datasheet States Can Wake From S1–S5 PCI_EXP_WAKE bit (Note 3) Must use the PCI Express* WAKE# pin rather than messages S1 for wake from S3,S4 ...
Page 172
... Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 70. Transitions Due to Power Failure State at Power Failure S0, S1 172 AFTERG3_EN bit Transition When Power Returns Functional Description - ® Intel ICH8 Family Datasheet ...
Page 173
... If both the THTL_EN and FORCE_THTL bits are set, then the ICH8 should use the duty cycle defined by the THRM_DTY field, not the THTL_DTY field. 5.13.8.4 Active Cooling Active cooling involves fans. The GPIO signals from the ICH8 can be used to turn on/off a fan. ® Intel ICH8 Family Datasheet 173 ...
Page 174
... Wake Event. Transitions to S0 state None Unconditional transition to S5 state Functional Description Table 71. Comment Software typically initiates a Sleep state Standard wakeup No effect since no power Not latched nor detected No dependence on processor (e.g., Stop-Grant cycles) or any other subsystem ® Intel ICH8 Family Datasheet ...
Page 175
... S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. ® Intel ICH8 Family Datasheet Event RI_EN ...
Page 176
... C3 state, the BMBUSY# signal is active, then the BM_STS bit will be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH8 will treat this as if one of the PCI REQ# signals went active. This is treated as a break event. 176 Functional Description ® Intel ICH8 Family Datasheet ...
Page 177
... Write Only Registers with Read Paths in ALT Access Mode The registers described in number field in the table indicates which register will be returned per access to that port. ® Intel ICH8 Family Datasheet Table 73 have read paths in ALT access mode. The access 177 ...
Page 178
... DMA Chan 5 base address low 1 byte DMA Chan 5 base address 2 high byte DMA Chan 5 base count low 1 byte DMA Chan 5 base count high 2 byte DMA Chan 6 base address low 1 byte DMA Chan 6 base address 2 high byte ® Intel ICH8 Family Datasheet ...
Page 179
... Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in ® Intel ICH8 Family Datasheet I Data ...
Page 180
... Cutting power to the memory may be done via the power supply external FETs to the motherboard. SLP_M# output signal can be used to cut power to the Link Controller, Clock chip or SPI flash on a platform that supports Intel AMT. 180 Value Returned 000 ...
Page 181
... PWROK from the main power supply. ICH8 has no dependency on the order in which these two signals go active or inactive. However, platforms that use the VRMPWRGD signal to start the clock chip PLLs assume that it does assert milliseconds before PWROK in order to provide valid clocks in time for the PWROK rising. ® Intel ICH8 Family Datasheet 181 ...
Page 182
... Clock to ICH8. This is not the system PCI clock. This Generator clock must keep running in S0 while the system PCI clock may stop based on CLKRUN# protocol. Stopped based on SLP_S3# assertion. Used by USB controllers and Intel Main Clock Audio controller. Stopped based on Generator SLP_S3# assertion. ...
Page 183
... Functional Description 5.13.12.1 Clock Control Signals from Intel Synthesizer (Mobile Only) The clock generator is assumed to have direct connect from the following ICH8 signals: • STP_CPU#: Stops processor clocks in C3 and C4 states • STP_PCI#: Stops system PCI clocks (not the ICH8 free-running 33 MHz clock) due to CLKRUN# protocol • ...
Page 184
... The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. 184 Functional Description Section 7.1.71) ® Intel ICH8 Family Datasheet ...
Page 185
... TCO Modes 5.14.2.1 TCO Legacy/Compatible Mode In TCO Legacy/Compatible mode the Intel Management Engine and Intel AMT logic and SMBus controllers are disabled. To enable Legacy/Compatible TCO mode the TCOMODE bit 7 in the ICHSTRP0 register in the SPI device must be 0. See details. ...
Page 186
... Table 77. TCO Legacy/Compatible Mode SMBus Configuration In TCO Legacy/Compatible mode the Intel ICH8/ICH8M can function directly with the integrated Gigabit Ethernet controller or equivalent external LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state ...
Page 187
... See Figure below. This mode is enabled when the BMCMODE bit 15 in the ICHSTRP0 register in the SPI device is 0. See The Intel AMT SMBus Controller 2 can be connected to either the SMBus pins or the SMLink pins by the MESM2SEL bit 23 in the ICHSTRP0 register in the SPI device. See Section 20 ...
Page 188
... Controller 2 Intel Controller 1 Host SMBus TCO Slave 188 Advanced TCO BMC Mode ICH8 ® AMT SMBus ® AMT SMLink SMBus BMC SMBus Legacy Sensors (Master or Slave with ALERT) Functional Description SPD (Slave) ASF Sensors (Master or Slave) ® Intel ICH8 Family Datasheet ...
Page 189
... If IORDY is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. If IORDY is negated when the initial sample point is reached, additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least two additional PCI clocks are added. ® Intel ICH8 Family Datasheet 189 ...
Page 190
... IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. Only 16-bit buffer writes are supported. 190 Table IORDY Startup Recovery Time Sample Latency (RCT) Point (ISP 2–5 1–4 Intel Functional Description 79. Shutdown Latency ® ICH8 Family Datasheet ...
Page 191
... Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. Figure 13. Physical Region Descriptor Table Entry Byte 3 Memory Region Physical Base Address [31:1] EOT Reserved ® Intel ICH8 Family Datasheet Byte 2 Byte 1 Byte 0 Byte Count [15:1] Main Memory Memory Region ...
Page 192
... At the end of the transfer, the IDE device signals an interrupt response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the controller status followed by the drive status to determine if the transfer completed successfully. 192 Functional Description ® Intel ICH8 Family Datasheet ...
Page 193
... Count) can be used to determine how much of the transfer was completed and to construct a new PRD table to complete the requested operation. In most cases the existing PRD table can be used to complete the operation. ® Intel ICH8 Family Datasheet Description DMA transfer is in progress. No interrupt has been generated by the IDE device ...
Page 194
... IDE channel Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD. 194 reads) providing data and toggling STROBE. Data is transferred – Functional Description – ® Intel ICH8 Family Datasheet ...
Page 195
... If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating that a trap occurred. ® Intel ICH8 Family Datasheet Section 12.1.56) contain control for generating 195 ...
Page 196
... ICH8 (AHCI/ RAID Disabled) N/A N/A N/A N/A Supported N/A N/A Supported N/A N/A N/A Functional Description ICH8 (AHCI/ RAID Enabled) Supported Supported Supported Supported Supported Supported Supported (Mobile Only) Supported N/A N/A Supported (Desktop Only) ® Intel ICH8 Family Datasheet ...
Page 197
... The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. ® Intel ICH8 Family Datasheet Description Allows the device to reorder commands for more efficient data ...
Page 198
... RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. By using the ICH8’s built-in Intel Matrix Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. ® ...
Page 199
... Intel Matrix Storage Manager RAID Option ROM The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: • Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & ...
Page 200
... Power ® Intel ICH SATA Controller = D0 Device = D0 Device = D1 PHY = PHY = PHY = PHY = PHY = Slumber Off (port Partial Slumber Off (port disabled) disabled) Resume Latency State HOT Functional Description Device = D3 PHY = PHY = Slumber Off (port disabled) ® Intel ICH8 Family Datasheet ...