UART, 16BYTE FIFO, 16C550, PLCC44

SC16C550BIA44

Manufacturer Part NumberSC16C550BIA44
DescriptionUART, 16BYTE FIFO, 16C550, PLCC44
ManufacturerNXP Semiconductors
SC16C550BIA44 datasheet
 

Specifications of SC16C550BIA44

No. Of Channels1Data Rate3Mbps
Supply Voltage Range2.25V To 5.5VOperating Temperature Range-40°C To +85°C
Digital Ic Case StylePLCCNo. Of Pins44
SvhcNo SVHC (18-Jun-2010)OperatingRoHS Compliant
Uart FeaturesAutomatic Hardware Flow Control, Software Selectable Baud Rate GeneratorRohs CompliantYes
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Rev. 05 — 1 October 2008
1. General description
The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for
serial data communications. Its principal function is to convert parallel data into serial
data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it
will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides
DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals
(TXRDY and RXRDY are not supported in the HVQFN32 package). On-board status
registers provide the user with error indications, operational status, and modem interface
control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range,
and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.
2. Features
I
5 V, 3.3 V and 2.5 V operation
I
Industrial temperature range
I
After reset, all registers are identical to the typical 16C450 register set
I
Capable of running with all existing generic 16C450 software
I
Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550
I
Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V
I
5 V tolerant on input only pins
I
16 byte transmit FIFO
I
16 byte receive FIFO with error flags
I
Programmable auto-RTS and auto-CTS
N
In auto-CTS mode, CTS controls transmitter
N
In auto-RTS mode, RX FIFO contents and threshold control RTS
I
Automatic hardware flow control
I
Software selectable baud rate generator
I
Four selectable Receive FIFO interrupt trigger levels
I
Standard modem interface
I
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
I
Independent receiver clock input
I
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
1.
For data bus pins D7 to D0, see
1
Table 24 “Limiting
values”.
Product data sheet

SC16C550BIA44 Summary of contents

  • Page 1

    SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Rev. 05 — 1 October 2008 1. General description The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is ...

  • Page 2

    ... Loopback controls for communications link fault isolation I Prioritized interrupt system controls I Modem control functions (CTS, RI, DCD, DSR, DTR, RTS) 3. Ordering information Table 1. Ordering information Industrial 2 Type number Package Name SC16C550BIA44 PLCC44 SC16C550BIBS HVQFN32 SC16C550BIB48 LQFP48 SC16C550BIN40 DIP40 SC16C550B_5 Product data sheet 2-stop bit +85 C ...

  • Page 3

    ... NXP Semiconductors 4. Block diagram SC16C550B DATA BUS IOR, IOR AND IOW, IOW CONTROL RESET LOGIC REGISTER CS0, CS1, CS2 SELECT LOGIC AS DDIS INT TXRDY RXRDY INTERRUPT CONTROL LOGIC Fig 1. Block diagram of SC16C550B SC16C550B_5 Product data sheet 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs ...

  • Page 4

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. SC16C550B_5 Product data sheet RCLK RX 11 SC16C550BIA44 n. CS0 CS1 15 CS2 16 17 BAUDOUT Pin configuration for PLCC44 terminal 1 index area n. SC16C550BIBS Transparent top view Pin configuration for HVQFN32 Rev. 05 — 1 October 2008 SC16C550B ...

  • Page 5

    ... NXP Semiconductors Fig 4. Fig 5. SC16C550B_5 Product data sheet n. RCLK 5 n.c. 6 SC16C550BIB48 CS0 9 10 CS1 CS2 11 BAUDOUT 12 Pin configuration for LQFP48 RCLK SC16C550BIN40 CS0 CS1 13 CS2 14 15 BAUDOUT XTAL1 16 XTAL2 17 IOW 18 19 IOW Pin configuration for DIP40 Rev. 05 — 1 October 2008 SC16C550B ...

  • Page 6

    ... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin PLCC44 LQFP48 DIP40 HVQFN32 BAUDOUT 17 12 [2] CS0 14 9 [2] CS1 15 10 [2] CS2 [2] CTS 47, 46 45, 44, 43 [2] DCD 42 40 DDIS 26 22 SC16C550B_5 Product data sheet Type Description Register select are used during read and write ...

  • Page 7

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 HVQFN32 [2] DSR 41 39 DTR 37 33 INT 33 30 n. 13, 23, 34 21, 25, 36, 37, 48 OUT1 38 34 OUT2 35 31 RCLK 10 5 IOR 25 20 [2] IOR 24 19 RESET 39 35 SC16C550B_5 Product data sheet Type ...

  • Page 8

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 HVQFN32 [ RTS 36 32 RXRDY TXRDY SC16C550B_5 Product data sheet Type Description Ring indicator modem status signal. Its condition can be checked by reading bit 6 (RI) of the Modem Status Register. Bit 2 ( RI) of the Modem Status Register indicates that RI has changed from a LOW to a HIGH level since the last read from the Modem Status Register ...

  • Page 9

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 HVQFN32 IOW 21 17 [2] IOW 20 16 XTAL1 18 14 [3] XTAL2 19 15 [1] HVQFN32 package die supply ground is connected to both the V supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the Printed-Circuit Board (PCB) in the thermal pad region ...

  • Page 10

    ... NXP Semiconductors 6.1 Internal registers The SC16C550B provides 12 internal registers for monitoring and control. These registers are shown in interrupt status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...

  • Page 11

    ... NXP Semiconductors 6.3 Autoflow control Autoflow control is comprised of auto-CTS and auto-RTS (see the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data ...

  • Page 12

    ... NXP Semiconductors 6.3.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 5. MCR[ 6.3.4 Auto-CTS and auto-RTS functional timing Start bits CTS (1) When CTS is LOW, the transmitter keeps sending serial data out. (2) If CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but it does not send the next byte ...

  • Page 13

    ... NXP Semiconductors RX byte 14 RTS released after the RTS first data bit of byte 16 IOR (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte. (2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) When the receive FIFO is full, the fi ...

  • Page 14

    ... NXP Semiconductors 6.5 Programmable baud rate generator The SC16C550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460 ...

  • Page 15

    ... NXP Semiconductors Table 6. Using 1.8432 MHz crystal Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 6.6 DMA operation The SC16C550B FIFO trigger level provides additional flexibility to the user for block mode operation ...

  • Page 16

    ... NXP Semiconductors 6.7 Loopback mode The internal loopback capability allows on-board diagnostics. In the loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally. MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the loopback mode, OUT1 (bit 2) and OUT2 (bit 3) in the MCR register control the modem RI and DCD inputs, respectively ...

  • Page 17

    ... NXP Semiconductors SC16C550B DATA BUS IOR, IOR AND IOW, IOW CONTROL RESET LOGIC REGISTER SELECT CS0, CS1, CS2 LOGIC AS DDIS INT INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 11. Internal loopback mode diagram SC16C550B_5 Product data sheet 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs ...

  • Page 18

    ... NXP Semiconductors 7. Register descriptions Table 9 The assigned bit functions are more fully defined in Table 9. SC16C550B internal registers Register Default [1] [2] General Register Set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [5] Special Register Set DLL DLM XX [1] The value shown represents the register’s initialized hexadecimal value not applicable. ...

  • Page 19

    ... NXP Semiconductors 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the THR, providing that the THR or TSR is empty. The THR empty fl ...

  • Page 20

    ... NXP Semiconductors 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level ...

  • Page 21

    ... NXP Semiconductors 7.3.2 FIFO mode Table 11. Bit 7:6 5 SC16C550B_5 Product data sheet FIFO Control Register bits description Symbol Description FCR[7] (MSB), RX trigger. These bits are used to set the trigger level for the receive FCR[6] (LSB) FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level ...

  • Page 22

    ... NXP Semiconductors Table 12. FCR[ 7.4 Interrupt Status Register (ISR) The SC16C550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...

  • Page 23

    ... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Bit 1:0 SC16C550B_5 Product data sheet ...

  • Page 24

    ... NXP Semiconductors Table 16. LCR[ Table 17. LCR[ Table 18. LCR[ SC16C550B_5 Product data sheet LCR[5] parity selection LCR[4] LCR[3] Parity selection parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ forced parity ‘0’ LCR[2] stop bit length Word length ...

  • Page 25

    ... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Bit SC16C550B_5 Product data sheet Modem Control Register bits description Symbol Description MCR[7] reserved; set to ‘0’ MCR[6] reserved; set to ‘0’ ...

  • Page 26

    ... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C550B and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C550B_5 Product data sheet Line Status Register bits description Description FIFO data error ...

  • Page 27

    ... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...

  • Page 28

    ... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C550B external reset conditions Table 22. Register IER ISR LCR MCR LSR MSR FCR Table 23. Output TX RTS DTR RXRDY TXRDY 8. Limiting values Table 24. In accordance with the Absolute Maximum Rating System (IEC 60134). ...

  • Page 29

    ... NXP Semiconductors 9. Static characteristics Table 25. Static characteristics +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input voltage IL(clk) V clock HIGH-level input voltage IH(clk) V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage OH I LOW-level input leakage ...

  • Page 30

    Table 26. Dynamic characteristics +85 C; tolerance unless otherwise specified. amb DD Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f clock frequency XTAL t address strobe ...

  • Page 31

    Table 26. Dynamic characteristics …continued +85 C; tolerance unless otherwise specified. amb DD Symbol Parameter t delay from stop to set interrupt 20d t delay from IOR to reset interrupt 21d ...

  • Page 32

    ... NXP Semiconductors 10.1 Timing diagrams CS2 CS1, CS0 t 8d IOR, IOR DDIS Fig 12. General read timing when using AS signal CS2 CS1, CS0 t 14d IOW, IOW Fig 13. General write timing when using AS signal SC16C550B_5 Product data sheet t 5h valid address valid active ...

  • Page 33

    ... NXP Semiconductors 6s' CS IOR Fig 14. General read timing when AS is tied 6s' CS IOW Fig 15. General write timing when AS is tied to V SC16C550B_5 Product data sheet 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs valid address t 7h' active active t 12h t 12d data ...

  • Page 34

    ... NXP Semiconductors IOW active RTS change of state DTR DCD CTS DSR INT IOR RI Fig 16. Modem input/output timing EXTERNAL CLOCK ------- XTAL t w3 Fig 17. External clock timing SC16C550B_5 Product data sheet 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs t 17d change of state t 18d ...

  • Page 35

    ... NXP Semiconductors RX INT IOR Fig 18. Receive timing RX RXRDY IOR Fig 19. Receive ready timing in non-FIFO mode SC16C550B_5 Product data sheet start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock start bit data bits ( Rev. 05 — 1 October 2008 SC16C550B ...

  • Page 36

    ... NXP Semiconductors RX RXRDY IOR Fig 20. Receive ready timing in FIFO mode TX INT active IOW Fig 21. Transmit timing SC16C550B_5 Product data sheet start bit data bits ( start bit data bits ( data bits 6 data bits 7 data bits active transmitter ready t 22d t 23d 16 baud rate clock Rev. 05 — ...

  • Page 37

    ... NXP Semiconductors TX active IOW byte #1 TXRDY Fig 22. Transmit ready timing in non-FIFO mode TX IOW active byte #16 TXRDY Fig 23. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C550B_5 Product data sheet start bit data bits ( 27d active transmitter ready start bit data bits ( ...

  • Page 38

    ... NXP Semiconductors 11. Package outline DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 4 inches 0.19 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 39

    ... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 40

    ... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT313-2 136E05 Fig 26 ...

  • Page 41

    ... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 42

    ... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 43

    ... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 44

    ... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Soldering of through-hole mount packages 13.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...

  • Page 45

    ... NXP Semiconductors 13.4 Package related soldering information Table 29. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. ...

  • Page 46

    ... NXP Semiconductors 15. Revision history Table 31. Revision history Document ID Release date SC16C550B_5 20081001 • Modifications: changed all occurrences of “V • Section 2 • Table 2 “Pin the CPU is not reading data. When active, DDIS can disable an external transceiver.” to “DDIS is active (LOW) when the CPU is reading data. When inactive (HIGH), DDIS can disable an external transceiver.” ...

  • Page 47

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 48

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Internal registers 6.2 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Autoflow control . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.3 Enabling autoflow control and auto-CTS . . . . 12 6 ...