SC16C750BIB64 NXP Semiconductors, SC16C750BIB64 Datasheet

UART, 64BYTE FIFO, 16C750, LQFP64

SC16C750BIB64

Manufacturer Part Number
SC16C750BIB64
Description
UART, 64BYTE FIFO, 16C750, LQFP64
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C750BIB64

No. Of Channels
1
Data Rate
3Mbps
Supply Voltage Range
2.25V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (18-Jun-2010)
Operating
RoHS Compliant
Uart Features
Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
Rohs Compliant
Yes

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1. General description
2. Features
1.
For data bus pins D7 to D0, see
The SC16C750B is a Universal Asynchronous Receiver and Transmitter (UART) used for
serial data communications. Its principal function is to convert parallel data into serial
data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C750B is pin compatible with the TL16C750 and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C750B. Some of these added features are the 64-byte receive
and transmit FIFOs, automatic hardware flow control. The selectable auto-flow control
feature significantly reduces software overload and increases system efficiency while in
FIFO mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C750B also provides DMA mode data transfers through FIFO trigger
levels and the TXRDY and RXRDY signals. On-board status registers provide the user
with error indications, operational status, and modem interface control. System interrupts
may be tailored to meet user requirements. An internal loopback capability allows
on-board diagnostics.
The SC16C750B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range and is
available in plastic PLCC44, LQFP64, and HVQFN32 packages.
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SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Rev. 05 — 17 October 2008
Single channel
5 V, 3.3 V and 2.5 V operation
5 V tolerant on input only pins
Industrial temperature range ( 40 C to +85 C)
After reset, all registers are identical to the typical 16C450 register set
Capable of running with all existing generic 16C450 software
Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with SC16C750 and TL16C750
Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V
64-byte transmit FIFO
64-byte receive FIFO with error flags
Programmable auto-RTS and auto-CTS
Automatic hardware flow control
Software selectable baud rate generator
N
N
In auto-CTS mode, CTS controls transmitter
In auto-RTS mode, receive FIFO contents and threshold control RTS
Table 24 “Limiting
values”.
1
Product data sheet

Related parts for SC16C750BIB64

SC16C750BIB64 Summary of contents

Page 1

SC16C750B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 05 — 17 October 2008 1. General description The SC16C750B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is ...

Page 2

... Prioritized interrupt system controls I Modem control functions (CTS, RTS, DSR, DTR, RI, DCD) 3. Ordering information Table 1. Ordering information Industrial 2 Type number Package Name SC16C750BIA44 PLCC44 SC16C750BIB64 LQFP64 SC16C750BIBS HVQFN32 SC16C750B_5 Product data sheet 2-stop bit +85 C. amb Description plastic leaded chip carrier; 44 leads plastic low profi ...

Page 3

... NXP Semiconductors 4. Block diagram SC16C750B DATA BUS IOR, IOR IOW, IOW CONTROL RESET LOGIC REGISTER CS0, CS1, CS2 SELECT AS LOGIC DDIS INT INTERRUPT TXRDY CONTROL RXRDY LOGIC Shown for PLCC44 and LQFP64 pin assignments. Fig 1. Block diagram of SC16C750B SC16C750B_5 Product data sheet ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. SC16C750B_5 Product data sheet RCLK RX 11 SC16C750BIA44 n. CS0 CS1 15 CS2 16 17 BAUDOUT Pin configuration for PLCC44 terminal 1 index area RCLK 4 SC16C750BIBS BAUDOUT 8 Transparent top view Pin configuration for HVQFN32 Rev. 05 — 17 October 2008 SC16C750B ...

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... CS2 SC16C750B_5 Product data sheet 1 XTAL1 XTAL2 2 n.c. 3 IOW 4 5 n.c. IOW 6 n. GND SC16C750BIB64 IOR 9 IOR 10 n. DDIS TXRDY 13 n. n.c. Pin configuration for LQFP64 Type Description HVQFN32 16, 17 Register select are used during read and write operations to select the UART register to read from or write to. ...

Page 6

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP64 CTS 52, 51, 50 48, 46, 45 43, 42 DCD 42 36 DDIS 26 12 DSR 41 35 DTR 37 28 INT 11, 14, 16, 19, 22, 24, 27, 29, 31, 34, 37, 39, 41, 44, 47, 49, 53, 56, 57, 60, 63 OUT1, 38, 35 30, 25 OUT2 OUT ...

Page 7

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP64 RCLK 10 54 RESET 39 32 IOR 25 10 IOR RTS 36 26 RXRDY SC16C750B_5 Product data sheet Type Description HVQFN32 4 I Receiver clock. RCLK is the 16 baud rate clock for the receiver section of the UART. ...

Page 8

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC44 LQFP64 TXRDY GND 22 8 IOW 21 6 IOW 20 4 XTAL1 18 1 [1] XTAL2 19 2 [1] In Sleep mode, XTAL2 is left floating. 6. Functional description The SC16C750B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections ...

Page 9

... NXP Semiconductors The rich feature set of the SC16C750B is available through internal registers. Automatic hardware flow control, selectable transmit and receive FIFO trigger level, selectable TX and RX baud rates, modem interface controls, and a sleep mode are some of these features. 6.1 Internal registers The SC16C750B provides 12 internal registers for monitoring and control. These registers are shown in standard 16C550 ...

Page 10

... NXP Semiconductors 6.2 FIFO operation The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached ...

Page 11

... NXP Semiconductors 6.5 Programmable baud rate generator The SC16C750B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460 ...

Page 12

... NXP Semiconductors Table 5. Using 1.8432 MHz crystal Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 6.6 DMA operation The SC16C750B FIFO trigger level provides additional flexibility to the user for block mode operation ...

Page 13

... NXP Semiconductors 6.7 Sleep mode The SC16C750B is designed to operate with low power consumption. A special Sleep mode is included to further reduce power consumption (the internal oscillator driver is disabled) when the chip is not being used. With IER[4] enabled (set to a logic 1), the SC16C750B enters the Sleep mode, but resumes normal operation when a start bit is detected, a change of state any of the modem input pins RI, CTS, DSR, DCD transmit data is provided by the user ...

Page 14

... NXP Semiconductors SC16C750B DATA BUS IOR, IOR AND IOW, IOW CONTROL RESET LOGIC REGISTER CS0, CS1, CS2 SELECT AS LOGIC DDIS INT INTERRUPT TXRDY CONTROL RXRDY LOGIC Shown for PLCC44 and LQFP64 pin assignments. Fig 6. Internal Loopback mode diagram SC16C750B_5 Product data sheet ...

Page 15

... NXP Semiconductors 7. Register descriptions Table 8 assigned bit functions are more fully defined in Table 8. SC16C750B internal registers Register Default [2] General Register Set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [3] Special Register Set DLL DLM XX [1] The value shown represents the register’s initialized HEX value n/a. ...

Page 16

... NXP Semiconductors 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty. The THR empty fl ...

Page 17

... NXP Semiconductors Table 9. Bit Symbol 1 IER[1] 0 IER[0] 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level ...

Page 18

... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode ...

Page 19

... NXP Semiconductors Table 10. Bit Symbol FCR[3] (continued) 2 FCR[2] 1 FCR[1] 0 FCR[0] Table 11. FCR[ SC16C750B_5 Product data sheet FIFO Control Register bits description Description Transmit operation in mode ‘1’: When the SC16C750B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full ...

Page 20

... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C750B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...

Page 21

... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 14. Bit 1:0 SC16C750B_5 Product data sheet ...

Page 22

... NXP Semiconductors Table 15. LCR[ Table 16. LCR[ Table 17. LCR[ SC16C750B_5 Product data sheet LCR[5] parity selection LCR[4] LCR[3] Parity selection parity 0 1 odd parity 1 1 even parity 0 1 force parity ‘1’ forced parity ‘0’ LCR[2] stop bit length Word length (bits) ...

Page 23

... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Bit The flow control can be configured by programming MCR[1] and MCR[5] as shown in Table 19. Table 19. MCR[5] (AFE SC16C750B_5 Product data sheet Modem Control Register bits description ...

Page 24

... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C750B and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C750B_5 Product data sheet Line Status Register bits description Description FIFO data error ...

Page 25

... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C750B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...

Page 26

... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C750B provides a temporary data register to store 8 bits of user information. 7.10 SC16C750B external reset conditions Table 22. Register IER ISR LCR MCR LSR MSR FCR Table 23. Output TX RTS DTR RXRDY TXRDY INT 8. Limiting values Table 24. ...

Page 27

... NXP Semiconductors 9. Static characteristics Table 25. Static characteristics +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input voltage IL(clk) V clock HIGH-level input voltage IH(clk) V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage OH I LOW-level input leakage current ...

Page 28

... NXP Semiconductors 10. Dynamic characteristics Table 26. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f frequency on pin XTAL1 XTAL1 t address strobe width 4w t address set-up time 5s t address hold time 5h t chip select set-up time to AS ...

Page 29

... NXP Semiconductors Table 26. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from IOW to reset 24d interrupt t delay from stop to set RXRDY 25d t delay from IOR to reset 26d RXRDY t delay from IOW to set TXRDY 27d t delay from start to reset 28d TXRDY ...

Page 30

... NXP Semiconductors CS2 CS1, CS0 t 14d IOW, IOW Fig 8. General write timing when using AS signal 6s' CS IOR Fig 9. General read timing when AS is tied to GND SC16C750B_5 Product data sheet t 5h valid address valid t t 13d 13h t 13w t 15d active t t 16h ...

Page 31

... NXP Semiconductors 6s' CS IOW Fig 10. General write timing when AS is tied to GND active IOW RTS change of state DTR DCD CTS DSR INT IOR RI Fig 11. Modem input/output timing SC16C750B_5 Product data sheet 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs valid address ...

Page 32

... NXP Semiconductors EXTERNAL CLOCK ------- XTAL1 t w3 Fig 12. External clock timing RX INT IOR Fig 13. Receive timing SC16C750B_5 Product data sheet start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock Rev. 05 — 17 October 2008 SC16C750B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs ...

Page 33

... NXP Semiconductors RX RXRDY IOR Fig 14. Receive ready timing in non-FIFO mode RX RXRDY IOR Fig 15. Receive ready timing in FIFO mode SC16C750B_5 Product data sheet start bit data bits ( start bit data bits ( Rev. 05 — 17 October 2008 SC16C750B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs ...

Page 34

... NXP Semiconductors TX INT active IOW Fig 16. Transmit timing TX IOW active byte #1 TXRDY Fig 17. Transmit ready timing in non-FIFO mode SC16C750B_5 Product data sheet start bit data bits ( data bits 6 data bits 7 data bits active transmitter ready t 22d t 23d 16 baud rate clock start ...

Page 35

... NXP Semiconductors TX IOW active byte # byte #64 t 27d TXRDY Fig 18. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C750B_5 Product data sheet start bit data bits ( data bits 6 data bits 7 data bits t 28d FIFO full Rev. 05 — 17 October 2008 SC16C750B ...

Page 36

... NXP Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 37

... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 38

... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT314-2 136E10 Fig 21 ...

Page 39

... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 40

... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 41

... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 29. Acronym CMOS CPU DLL DLM DMA FIFO ISDN LSB MSB TTL UART ...

Page 42

... Release date SC16C750B_5 20081017 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 • Figure 3 “Pin configuration for • ...

Page 43

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 44

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 8 6.1 Internal registers 6.2 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Hardware flow control . . . . . . . . . . . . . . . . . . . 10 6.4 Time-out interrupts . . . . . . . . . . . . . . . . . . . . . 10 6.5 Programmable baud rate generator . . . . . . . . 11 6 ...

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