SC26C92A1A NXP Semiconductors, SC26C92A1A Datasheet - Page 5

• Manufacturer Part Number: SC26C92A1A
• Description: IC, UART, DUAL, SMD, 26C92, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SC26C92A1A

• No. Of Channels: 2
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature: RoHS Compliant
• Data Rate: 230.4Kilobaud
• Uart Features: Parity, Framing, & Overrun Error Detection, Start-End Break Interrupt/Status
• Rohs Compliant: Yes

Philips Semiconductors
PIN DESCRIPTION
2000 Jan 31
SYMBOL
SYMBOL
Dual universal asynchronous receiver/transmitter (DUART)
D0-D7
CEN
WRN
RDN
A0-A3
RESET
INTRN
X1/CLK
X2
RxDA
RxDB
TxDA
TxDB
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
IP4
IP5
IP6
V
GND
CC
40,44
PKG
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TYPE
PIN
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines
in the 3-State condition.
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed
register. The transfer occurs on the rising edge of the signal.
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the
High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (High) state. Sets MR pointer to MR1 and resets MR0.
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight
maskable interrupting conditions are true. Requires a pullup resistor.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used this pin must be left open or not driving
more than one TTL equivalent load.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is High, ‘space’ is Low.
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output.
Output 5: General purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output.
Output 7: General purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal
V
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal
V
Input 2: General purpose input or counter/timer external clock input. Pin has an internal V
supplying 1 to 4 A of current.
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
Power Supply: +5V supply input.
Ground
CC
CC
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
CC
CC
CC
CC
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
5
NAME AND FUNCTION
NAME AND FUNCTION
Product specification
SC26C92
CC
pull-up device