SC26C92A1A NXP Semiconductors, SC26C92A1A Datasheet - Page 9

IC, UART, DUAL, SMD, 26C92, PLCC44

SC26C92A1A

Manufacturer Part Number
SC26C92A1A
Description
IC, UART, DUAL, SMD, 26C92, PLCC44
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC26C92A1A

No. Of Channels
2
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
No. Of Pins
44
Svhc
No SVHC (18-Jun-2010)
Operating Temperature
RoHS Compliant
Data Rate
230.4Kilobaud
Uart Features
Parity, Framing, & Overrun Error Detection, Start-End Break Interrupt/Status
Rohs Compliant
Yes

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operating frequency for each receiver and transmitter can be
selected independently from the baud rate generator, the
counter/timer, or from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin.
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
or break condition and sends an assembled character to the CPU
via the receive FIFO. Three status bits (Break Received, Framing
and Parity Errors) are also FIFOed with each data character.
Input Port
The inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic or modem and DMA control.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50 s, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25 s (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25 s if
the transition occurs “coincident with the first sample pulse”. The
50 s time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25 s later.
All the IP pins have a small pull-up device that will source 1 to 4 A
of current from V
V
Output Port
The output ports are controlled from five places: the OPCR register,
SOPR, ROPR, the MR registers and the command register (CR).
The OPCR register controls the source of the data for the output
ports OP2 through OP7. The data source for output ports OP0 and
OP1 is controlled by the MR and CR registers. Normally the data
source for the OP pins is from the OPR register. The OP pin drive
the inverted level (complement) of the OPR register. Example:
when the SOPR is used to set the OPR bit to a logical 1 then the
associated OP pin will drive a logical 0.
The content of the OPR register is controlled by the “Set Output Port
Bits Command” and the “Reset Output Bits Command”. These com-
mands are at E and F, respectively. When these commands are
used, action takes place only at the bit locations where ones exist.
For example, a one in bit location 5 of the data word used with the
“Set Output Port Bits” command will result in OPR(5) being set to
one. The OP5 would then be set to zero (V
bit position 5 of the data word associated with the “Reset Output
Ports Bits” command would set OPR(5) to zero and, hence, the pin
OP5 to a one (Vdd).
Please note that these pins drive both high and low. However when
they are programmed to represent interrupt type functions (such as
2000 Jan 31
CC
Dual universal asynchronous receiver/transmitter (DUART)
connections if they are not used.
CC
. These pins do not require pull-up devices or
SS
). Similarly, a one in
9
RxRDY) they will be switched to an open drain configuration. In this
configuration an external pull–up device will be required
OPERATION
Transmitter
The SC26C92 is conditioned to transmit data when the transmitter is
enabled through the command register. The SC26C92 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP0, OP1 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMT bits will be set
in the status register. When a character is loaded to the transmit
FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re–enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the charac-
ter currently being transmitted and any characters in the TxFIFO
including parity and stop bit(s) have been completed.
Note the differences between the transmitter disable and the trans-
mitter reset: reset stops all transmission immediately, effectively
clears the TxFIFO and resets all status and Tx interrupt conditions.
Transmitter disable clears all Tx status and interrupts BUT allows
the Tx to complete the transmission of all data in the TxFIFO and in
the shift register. While the Tx is disabled the TxFIFO can not be
loaded with data.
The transmitter can be forced to send a continuous Low condition by
issuing a send break command from the command register. The
transmitter output is returned to the normal high with a stop break
command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If the CTS option is enabled (MR2[4] = 1), the CTSN input at IP0 or
IP1 must be low in order for the character to be transmitted. The
transmitter will check the state of the CTS input at the beginning of
each character transmitted. If it is found to be High, the transmitter
will delay the transmission of any following characters until the CTS
has returned to the low state. CTS going high during the serializa-
tion of a character will not affect that character.
Transmitter “RS485 turnaround”
The transmitter can also control the RTSN outputs, OP0 or OP1 via
MR2[5]. When this mode of operation is set, the meaning of the
OP0 and OP1 signal will usually be ‘end of message’. See
description of the MR2[5] bit for more detail.
Product specification
SC26C92

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