SCC68692C1A44 NXP Semiconductors, SCC68692C1A44 Datasheet - Page 9

• Manufacturer Part Number: SCC68692C1A44
• Description: UART, DUAL, SMD, 68692C1, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SCC68692C1A44

• No. Of Channels: 2
• Uart Features: Quadruple Buffered Receiver Data Register
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Data Rate: 115.2Kilobaud
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

missed” and the first change-of-state is not detected until 25 s later.
another parallel port to external circuits, or they may represent many
operation at address H’E’ with the accompanying data specifying the
ready, transmitter ready or counter/timer ready) they will be switched
then asserted again which means one full character time of buffering
Philips Semiconductors
Input Port
The inputs to this unlatched 6-bit port can be read by the CPU by
performing a read operation at address H’D’. A HIGH input results in
a logic 1 while a LOW input results in a logic 0. D7 will always be
read as a logic 1 and D6 will reflect the level of IP2. The pins of this
port can also serve as auxiliary inputs to certain portions of the
DUART logic.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH
transition of these inputs, lasting longer than 25 – 50 s, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port pulse detection circuitry uses a 38.4 kHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25 s (this assumes that
the clock input is 3.6864 MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25 s if
the transition occurs “coincident with the first sample pulse”. The
50 s time refers to the situation in which the change-of-state is “just
All the IP pins have a small pull-up device that will source 1 to 4 A
of current from V
V
Output Port
The output port pins may be controlled by the OPR, OPCR, MR and
the CR registers. Via appropriate programming they may be just
internal conditions of the UART. When this 8-bit port is used as a
general purpose output port, the output port pins assume a state
which is the complement of the Output Port Register (OPR).
OPR(n) = 1 results in OP(n) = LOW and vice versa. Bits of the OPR
can be individually set and reset. A bit is set by performing a write
bits to be reset (1 = set, 0 = no change). Likewise, a bit is reset by a
write at address H’F’ with the accompanying data specifying the bits
to be reset (1 = reset, 0 = no change).
Outputs can be also be individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Output ports are driven HIGH on hardware reset. Please note that
these pins drive both HIGH and LOW. However when they are
programmed to represent interrupt type functions (such as receiver
to an open drain configuration in which case an external pull-up
device would be required.
OPERATION
Transmitter
The SCC68692 is conditioned to transmit data when the transmitter
is enabled through the command register. The SCC68692 indicates
to the CPU that it is ready to accept a character by setting the
TxRDY bit in the status register. This condition can be programmed
to generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
2004 Mar 03
CC
Dual asynchronous receiver/transmitter (DUART)
connections if they are not used.
CC
. These pins do not require pull-up devices or
9
enabled through the command register before resuming operation. If
The SCC68692 is conditioned to receive data when enabled through
the bit time clock (1X clock mode). If RxD is sampled HIGH, the start
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains HIGH
and the TxEMT bit in the Status Register (SR) will be set to ‘1’.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR. If the transmitter is disabled, it
continues operating until the character currently being transmitted is
completely sent out. The transmitter can be forced to send a
continuous LOW condition by issuing a send break command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
CTS operation is enable, the CTSN input must be LOW in order for
the character to be transmitted. If it goes HIGH in the middle of a
transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes LOW. The
transmitter can also control the deactivation of the RTSN output. If
programmed, the RTSN output will be reset one bit time after the
character in the transmit shift register and transmit holding register
(if any) are completely transmitted, if the transmitter has been
disabled.
Receiver
the command register. The receiver looks for a HIGH-to-LOW
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
bit is invalid and the search for a valid start bit begins again. If RxD
is still LOW, a valid start bit is assumed and the receiver continues
to sample the input at one bit time intervals at the theoretical center
of the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a ‘1’. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains LOW for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is LOW for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to ‘1’. The RxD input must return to HIGH for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a HIGH time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
SCC68692
Product data