DSPIC30F5011-30I/PTG Microchip Technology, DSPIC30F5011-30I/PTG Datasheet
DSPIC30F5011-30I/PTG
Specifications of DSPIC30F5011-30I/PTG
Related parts for DSPIC30F5011-30I/PTG
DSPIC30F5011-30I/PTG Summary of contents
Page 1
... Microchip Technology Inc. Data Sheet High-Performance Digital Signal Controllers Preliminary DS70116C ...
Page 2
... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... High Performance Digital Signal Controllers High Performance Modified RISC CPU: • Modified Harvard architecture • C compiler optimized instruction set architecture • Flexible addressing modes • 84 base instructions • 24-bit wide instructions, 16-bit wide data path • 66 Kbytes on-chip Flash program space • ...
Page 4
... Controller Family Program Memory Device Pins Bytes Instructions dsPIC30F5011 64 66K 22K dsPIC30F5013 80 66K 22K Pin Diagrams 64-Pin TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: Pinout subject to change. ...
Page 5
... SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: Pinout subject to change. Note: For descriptions of individual pins, see Section 1.0. 2004 Microchip Technology Inc. dsPIC30F5011/5013 dsPIC30F5013 Preliminary EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS ...
Page 6
... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 CPU Architecture Overview........................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 21 4.0 Address Generator Units ............................................................................................................................................................ 33 5.0 Interrupts .................................................................................................................................................................................... 39 6.0 Flash Program Memory .............................................................................................................................................................. 45 7.0 Data EEPROM Memory ............................................................................................................................................................. 51 8.0 I/O Ports ..................................................................................................................................................................................... 57 9.0 Timer1 Module ........................................................................................................................................................................... 63 10.0 Timer2/3 Module ........................................................................................................................................................................ 67 11.0 Timer4/5 Module ........................................................................................................................................................................ 73 12.0 Input Capture Module ................................................................................................................................................................. 77 13 ...
Page 7
... Digital Signal Controller (DSC) devices. The dsPIC30F5011/5013 devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F5011 and dsPIC30F5013 respectively. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Preliminary ...
Page 8
... FIGURE 1-1: dsPIC30F5011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
Page 9
... Timing OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low Voltage Detect CAN1, 12-bit ADC CAN2 Timers 2004 Microchip Technology Inc. dsPIC30F5011/5013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (4 Kbytes) (4 Kbytes) 16 Address Address Latch Latch RAGU ...
Page 10
... Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
Page 11
... REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2004 Microchip Technology Inc. dsPIC30F5011/5013 Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes ...
Page 12
... NOTES: DS70116C-page 10 Preliminary 2004 Microchip Technology Inc. ...
Page 13
... Table read and write instructions can be used to access all 24 bits of an instruction word. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms ...
Page 14
... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists 16-bit working registers (W0 through W15 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC) ...
Page 15
... DSP AccA Accumulators AccB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH 2004 Microchip Technology Inc. dsPIC30F5011/5013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
Page 16
... Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2 ...
Page 17
... EDAC MAC MAC MOVSAC MPY MPY.N MSC 2004 Microchip Technology Inc. dsPIC30F5011/5013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
Page 18
... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70116C-page 16 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill 2004 Microchip Technology Inc. ...
Page 19
... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
Page 20
... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When satu- ...
Page 21
... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
Page 22
... NOTES: DS70116C-page 20 Preliminary 2004 Microchip Technology Inc. ...
Page 23
... In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. 2004 Microchip Technology Inc. dsPIC30F5011/5013 FIGURE 3-1: PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address ...
Page 24
... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using Program 0 Space Visibility Using ...
Page 25
... Program Memory ‘Phantom’ Byte (read as ‘0’) 2004 Microchip Technology Inc. dsPIC30F5011/5013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; ...
Page 26
... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MS BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
Page 27
... DSP instruc- tions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Program Space 0x0000 (1) PSVPAG 0x21 ...
Page 28
... When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64- Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64-Kbyte data address space excluding the Y address block (for data reads only) ...
Page 29
... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W 2004 Microchip Technology Inc. dsPIC30F5011/5013 SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
Page 30
... DATA SPACES The X data space is used by all instructions and sup- ports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
Page 31
... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. 2004 Microchip Technology Inc. dsPIC30F5011/5013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> ...
Page 32
... DS70116C-page 30 Preliminary 2004 Microchip Technology Inc. ...
Page 33
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 31 ...
Page 34
... NOTES: DS70116C-page 32 Preliminary 2004 Microchip Technology Inc. ...
Page 35
... MOV instruction allows additional flexibility and can access the entire data space during file register operation. 2004 Microchip Technology Inc. dsPIC30F5011/5013 4.1 Instruction Addressing Modes The addressing modes in Table 4-1 form the basis of the addressing modes optimized to support the specific features of individual instructions ...
Page 36
... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
Page 37
... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2004 Microchip Technology Inc. dsPIC30F5011/5013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
Page 38
... MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the effective address (EA) calculation associated with any W regis- ter important to realize that the address bound- aries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
Page 39
... BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 2004 Microchip Technology Inc. dsPIC30F5011/5013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary A0 Decimal ...
Page 40
... NOTES: DS70116C-page 38 Preliminary 2004 Microchip Technology Inc. ...
Page 41
... Microchip Technology Inc. dsPIC30F5011/5013 All interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the IPCx registers. Each interrupt source is associated with an interrupt vector, as shown in Table 5-1 ...
Page 42
... Interrupt Priority The user assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the LS 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
Page 43
... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. 2004 Microchip Technology Inc. dsPIC30F5011/5013 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...
Page 44
... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
Page 45
... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. 2004 Microchip Technology Inc. dsPIC30F5011/5013 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
Page 46
... DS70116C-page 44 Preliminary 2004 Microchip Technology Inc. ...
Page 47
... Addressing Using Table Instruction User/Configuration Space Select 2004 Microchip Technology Inc. dsPIC30F5011/5013 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
Page 48
... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...
Page 49
... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP 2004 Microchip Technology Inc. dsPIC30F5011/5013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
Page 50
... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
Page 51
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 49 ...
Page 52
... NOTES: DS70116C-page 50 Preliminary 2004 Microchip Technology Inc. ...
Page 53
... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. They are cleared in hardware at the com- range ...
Page 54
... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
Page 55
... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete 2004 Microchip Technology Inc. dsPIC30F5011/5013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
Page 56
... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV ...
Page 57
... This should be used in applications where excessive writes can stress bits near the specification limit. 2004 Microchip Technology Inc. dsPIC30F5011/5013 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
Page 58
... NOTES: DS70116C-page 56 Preliminary 2004 Microchip Technology Inc. ...
Page 59
... WR TRIS WR LAT + WR Port Read LAT Read Port 2004 Microchip Technology Inc. dsPIC30F5011/5013 When a pin is shared with another peripheral or func- tion that is defined as an input only nevertheless , MCLR and SS regarded as a dedicated port because there is no other competing source of outputs. An example is the INT4 pin ...
Page 60
... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Read Port 8.2 ...
Page 61
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 59 ...
Page 62
... DS70116C-page 60 Preliminary 2004 Microchip Technology Inc. ...
Page 63
... Sleep mode, when the clocks are disabled. There are exter- nal signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 8-10: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 15-8) SFR Addr. Bit 15 Bit 14 Name ...
Page 64
... NOTES: DS70116C-page 62 Preliminary 2004 Microchip Technology Inc. ...
Page 65
... SOSCO/ T1CK LPOSCEN SOSCI 2004 Microchip Technology Inc. dsPIC30F5011/5013 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register PR1, then resets to ‘0’ and continues to count. When the CPU goes into the Idle mode, the timer will stop incrementing unless the TSIDL (T1CON< ...
Page 66
... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
Page 67
... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
Page 68
... DS70116C-page 66 Preliminary 2004 Microchip Technology Inc. ...
Page 69
... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). 2004 Microchip Technology Inc. dsPIC30F5011/5013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode ...
Page 70
... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70116C-page 68 ...
Page 71
... Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK 2004 Microchip Technology Inc. dsPIC30F5011/5013 PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 TMR3 ...
Page 72
... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
Page 73
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 71 ...
Page 74
... NOTES: DS70116C-page 72 Preliminary 2004 Microchip Technology Inc. ...
Page 75
... Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. 2004 Microchip Technology Inc. dsPIC30F5011/5013 The Operating modes of the Timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs. For 32-bit timer/counter operation, Timer4 is the LS Word and Timer5 is the MS Word of the 32-bit timer ...
Page 76
... ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F5011 device, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: 1: TCS = 1 (16-bit counter) 2: TCS = 0, TGATE = 1 (gated time accumulation) DS70116C-page 74 PR4 Comparator x 16 TMR4 Q TGATE ...
Page 77
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 75 ...
Page 78
... NOTES: DS70116C-page 76 Preliminary 2004 Microchip Technology Inc. ...
Page 79
... Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM<2:0> (ICxCON<2:0>). 2004 Microchip Technology Inc. dsPIC30F5011/5013 The key operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
Page 80
... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE - Input Capture Buffer Not Empty • ICOV - Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO ...
Page 81
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 79 ...
Page 82
... NOTES: DS70116C-page 80 Preliminary 2004 Microchip Technology Inc. ...
Page 83
... Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. 2004 Microchip Technology Inc. dsPIC30F5011/5013 These Operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC devices contain compare channels (i ...
Page 84
... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
Page 85
... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. 2004 Microchip Technology Inc. dsPIC30F5011/5013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 86
... DS70116C-page 84 Preliminary 2004 Microchip Technology Inc. ...
Page 87
... SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit. 2004 Microchip Technology Inc. dsPIC30F5011/5013 In Slave mode, data is transmitted and received as external clock pulses appear on SCK. Again, the inter- rupt is generated when the last bit is latched. If SSx control is enabled, then transmission and reception are enabled only when SSx = low ...
Page 88
... FIGURE 14-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit 0 SDOx SS & FSYNC Control SSx SCKx Note FIGURE 14-2: SPI MASTER/SLAVE CONNECTION SPI™ Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note DS70116C-page 86 Internal Data Bus Write ...
Page 89
... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
Page 90
... DS70116C-page 88 Preliminary 2004 Microchip Technology Inc. ...
Page 91
... I2CRCV is the receive buffer as shown in Figure 15-1. I2CTRN is the transmit register to which bytes are written during a transmit operation, as shown in Figure 15-2. 2004 Microchip Technology Inc. dsPIC30F5011/5013 15.1 Operating Function Description The hardware fully implements all the master and slave functions of the I specifications, as well as 7 and 10-bit addressing ...
Page 92
... FIGURE 15- BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Start, RESTART, Stop bit Generate Shift Clock DS70116C-page 90 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down ...
Page 93
... If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are 2004 Microchip Technology Inc. dsPIC30F5011/5013 received, if I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock. ...
Page 94
... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 15.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...
Page 95
... Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2 15. Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition ...
Page 96
... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbi- tration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...
Page 97
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 95 ...
Page 98
... NOTES: DS70116C-page 96 Preliminary 2004 Microchip Technology Inc. ...
Page 99
... Data UxTX Parity Note 2004 Microchip Technology Inc. dsPIC30F5011/5013 • Fully integrated baud rate generator with 16-bit prescaler • Baud rates range from 38 bps to 1.875 Mbps MHz instruction rate • 4-word deep transmit data buffer • 4-word deep receive data buffer • ...
Page 100
... FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70116C-page 98 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 101
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). 2004 Microchip Technology Inc. dsPIC30F5011/5013 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 102
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 103
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. 2004 Microchip Technology Inc. dsPIC30F5011/5013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 104
... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. ...
Page 105
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 103 ...
Page 106
... NOTES: DS70116C-page 104 Preliminary 2004 Microchip Technology Inc. ...
Page 107
... Programmable link to timer module for time-stamping and network synchronization • Low power Sleep and Idle mode 2004 Microchip Technology Inc. dsPIC30F5011/5013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 108
... FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). DS70116C-page 106 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 ...
Page 109
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 110
... Message Reception 17.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 111
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 112
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt. • ...
Page 113
... The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg 2004 Microchip Technology Inc. dsPIC30F5011/5013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 114
... DS70116C-page 112 Preliminary 2004 Microchip Technology Inc. ...
Page 115
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 113 ...
Page 116
... DS70116C-page 114 Preliminary 2004 Microchip Technology Inc. ...
Page 117
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 115 ...
Page 118
... NOTES: DS70116C-page 116 Preliminary 2004 Microchip Technology Inc. ...
Page 119
... CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.2.3.1 COFS PIN The Codec frame synchronization (COFS) pin is used to synchronize data transfers that occur on the CSDO and CSDI pins ...
Page 120
... FIGURE 18-1: DCI MODULE BLOCK DIAGRAM F OSC Word Size Selection bits Frame Length Selection bits DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70116C-page 118 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer ...
Page 121
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the Frame Synchronization (COFSM< ...
Page 122
... SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sam- pled high (see Figure 18-2) ...
Page 123
... When the CSCK signal is applied exter- nally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.3.8 SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal ...
Page 124
... RECEIVE SLOT ENABLE BITS The RSCON SFR contains control bits that are used to enable time slots for reception. These control bits are the RSE<15:0> bits. The size of each receive time slot is determined by the WS<3:0> word size selection bits and can vary from bits. ...
Page 125
... DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.3.19 CSDO MODE BIT The CSDOM control bit controls the behavior of the CSDO pin during unused transmit slots. A given trans- mit time slot is unused if it’ ...
Page 126
... DCI Module Operation During CPU Sleep and Idle Modes 18.5.1 DCI MODULE OPERATION DURING CPU SLEEP MODE The DCI module has the ability to operate while in Sleep mode and wake the CPU when the CSCK signal is supplied by an external device (CSCKD = 1). The ...
Page 127
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 125 ...
Page 128
... NOTES: DS70116C-page 126 Preliminary 2004 Microchip Technology Inc. ...
Page 129
... AN14 1111 AN15 CH0G CH0R 2004 Microchip Technology Inc. dsPIC30F5011/5013 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 130
... A/D Result Buffer The module contains a 16-word dual port read only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 131
... 667 nsec (for V = 5V). Refer to the Electrical DD Specifications section for minimum T operating conditions. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Example 19-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 19-1: Minimum T ADCS<5:0> Therefore, Set ADCS< ...
Page 132
... A/D Acquisition Requirements The analog input model of the 12-bit A/D converter is shown in Figure 18-11. The total sampling time for the A function of the internal amplifier settling time and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, ...
Page 133
... Integer 0 2004 Microchip Technology Inc. dsPIC30F5011/5013 If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the D module will then be turned off, although the ADON bit will remain set ...
Page 134
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
Page 135
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 133 ...
Page 136
... NOTES: DS70116C-page 134 Preliminary 2004 Microchip Technology Inc. ...
Page 137
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. 2004 Microchip Technology Inc. dsPIC30F5011/5013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 138
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 139
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI 2004 Microchip Technology Inc. dsPIC30F5011/5013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock Switching Secondary Osc ...
Page 140
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> configuration bits that select one of four oscillator groups, b) and FPR<3:0> configuration bits that select one of 13 oscillator choices within the primary group. ...
Page 141
... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7.5 MHz. 2004 Microchip Technology Inc. dsPIC30F5011/5013 TABLE 20-4: TUN<3:0> Bits 0111 0110 0101 ...
Page 142
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 143
... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 144
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 145
... Specifications in the specific device data sheet for BOR voltage limit specifications. 2004 Microchip Technology Inc. dsPIC30F5011/5013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device configuration bit values (FOS<1:0> and FPR< ...
Page 146
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 147
... Illegal Operation Reset 0x000000 Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. 2004 Microchip Technology Inc. dsPIC30F5011/5013 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 148
... Watchdog Timer (WDT) 20.4.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software mal- function. The WDT is a free-running timer which runs off an on-chip RC oscillator, requiring no external com- ponent. Therefore, the WDT timer will continue to oper- ate even if the main processor clock (e ...
Page 149
... CPU and instruction execution begins immedi- ately, starting with the instruction following the PWRSAV instruction. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR ...
Page 150
... Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers pro- vide a method to disable a peripheral module by stop- ping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral minimum power consumption state ...
Page 151
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116C-page 149 ...
Page 152
... NOTES: DS70116C-page 150 Preliminary 2004 Microchip Technology Inc. ...
Page 153
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ 2004 Microchip Technology Inc. dsPIC30F5011/5013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: adds many • ...
Page 154
... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 155
... Y data space pre-fetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space pre-fetch destination register for DSP instructions 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0..W15} ...
Page 156
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 157
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 158
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DISI DISI #lit14 30 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 31 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 34 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 35 EXCH EXCH Wns,Wnd 36 FBCL FBCL Ws,Wnd 37 FF1L FF1L ...
Page 159
... RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 160
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 68 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 70 SETM SETM f SETM WREG SETM Ws 71 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 73 SUB SUB Acc ...
Page 161
... CAN ® - PowerSmart - Analog 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 162
... MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 163
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
Page 164
... PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program- mer or a PICSTART Plus development programmer ...
Page 165
... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 166
... NOTES: DS70116C-page 164 Preliminary 2004 Microchip Technology Inc. ...
Page 167
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table. 2004 Microchip Technology Inc. dsPIC30F5011/5013 (except V and MCLR) ................................................... -0. (Note 1) ......................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...
Page 168
... DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 23-2: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No ...
Page 169
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 170
... TABLE 23-3: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC27 — — DC27a TBD — DC27b — — DC27c — — DC27d TBD — DC27e — — DC27f — — DC28 — — DC28a TBD — ...
Page 171
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) (CONTINUED) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 172
... TABLE 23-4: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. Idle Current (I ): Core OFF Clock ON Base Current IDLE DC40 — — DC40a TBD — DC40b — — DC40c — — DC40d — — DC40e TBD — DC40f — — DC40g — ...
Page 173
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) (CONTINUED) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ...
Page 174
... TABLE 23-5: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power Down Current ( DC60 — — DC60a TBD — DC60b — — DC60c — — DC60d — — DC60e TBD — DC60f — — DC60g — — DC61 — ...
Page 175
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40°C T ...
Page 176
... TABLE 23-6: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 177
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C (1) Min Typ Max (2) — ...
Page 178
... TABLE 23-8: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD high to low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: ...
Page 179
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T (1) Min ...
Page 180
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin ...
Page 181
... Measurements are taken ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 182
... TABLE 23-13: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC OS53 D CLKOUT Stability (Jitter) CLK Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 183
... Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2004 Microchip Technology Inc. dsPIC30F5011/5013 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V ...
Page 184
... FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. ...
Page 185
... Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min ...
Page 186
... FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-19: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time ...
Page 187
... TxCK Input Period Synchronous, TC20 T Delay from External TQCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min Typ Synchronous, ...
Page 188
... FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 23-3 for load conditions. TABLE 23-22: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2004 Microchip Technology Inc. dsPIC30F5011/5013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 190
... FIGURE 23-12: DCI MODULE (MULTICHANNEL, I CSCK (SCKE = 1) CSCK (SCKE = 0) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. DS70116C-page 188 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 ...
Page 191
... The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2 S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 192
... FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 SYNC (COFS) CS80 MSb LSb SDO (CSDO) MSb IN SDI (CSDI) CS65 CS66 TABLE 23-26: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. CS60 T BIT_CLK Low Time ...
Page 193
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP21 SP20 BIT14 - - - - - -1 MSb SP30 BIT14 - - - -1 Standard Operating Conditions: 2 ...
Page 194
... FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) MSb SDO X SP40 SP30,SP31 SDI X MSb IN SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-28: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param ...
Page 195
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP20 SP20 MSb BIT14 - - - - - -1 SP30,SP31 ...
Page 196
... AC CHARACTERISTICS Param Symbol Characteristic No. SP52 TscH2ssH SS after SCK Edge X TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. ...
Page 197
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 198
... FIGURE 23-18 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 23-3 for load conditions. 2 FIGURE 23-19 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. ...
Page 199
... BRG is the value of the I C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ the dsPIC30F Family Reference Manual. 2: Maximum pin capacitance = 10 pF for all I 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T ...
Page 200
... FIGURE 23-20 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 23-21 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70116C-page 198 IS33 IS11 IS10 IS26 IS25 IS40 Preliminary ...