IC, LATTICEXP2 FPGA, 435MHZ, QFP-208

 

LFXP2-8E-5QN208C

Manufacturer Part NumberLFXP2-8E-5QN208C
DescriptionIC, LATTICEXP2 FPGA, 435MHZ, QFP-208
ManufacturerLATTICE SEMICONDUCTOR
SeriesLatticeXP2
LFXP2-8E-5QN208C datasheets

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Specifications of LFXP2-8E-5QN208C

No. Of Logic Blocks8000No. Of Macrocells4000
Family TypeLatticeXP2No. Of Speed Grades5
No. Of I/o's146Clock ManagementPLL
Total Ram Bits221KbitLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice0 through Slice2 Clock Selection
Secondary Clock
Figure 2-14. Slice0 through Slice2 Control Selection
Secondary Clock
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Primary Clock
8
4
25:1
Routing
12
Vcc
1
3
Routing
16:1
12
Vcc
1
2-14
Architecture
LatticeXP2 Family Data Sheet
Clock to Slice
Slice Control

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