LFXP2-8E-5QN208C | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5QN208C |
| Description | IC, LATTICEXP2 FPGA, 435MHZ, QFP-208 |
| Manufacturer | LATTICE SEMICONDUCTOR |
| Series | LatticeXP2 |
| LFXP2-8E-5QN208C datasheets |
|
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Specifications of LFXP2-8E-5QN208C | |||
|---|---|---|---|
| No. Of Logic Blocks | 8000 | No. Of Macrocells | 4000 |
| Family Type | LatticeXP2 | No. Of Speed Grades | 5 |
| No. Of I/o's | 146 | Clock Management | PLL |
| Total Ram Bits | 221Kbit | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can
be concatenated.
The resources in each sysDSP block can be configured to support the following four elements:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options: x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-6 shows the capabilities of the block.
Table 2-6. Maximum Number of Elements in a Block
Width of Multiply
MULT
MAC
MULTADDSUB
MULTADDSUBSUM
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. By selecting ‘dynamic operation’ the following operations
are possible:
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-20 shows the MULT sysDSP element.
x9
x18
8
4
2
2
4
2
2
1
2-19
Architecture
LatticeXP2 Family Data Sheet
x36
1
—
—
—
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