LFXP2-8E-5QN208C | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5QN208C |
| Description | IC, LATTICEXP2 FPGA, 435MHZ, QFP-208 |
| Manufacturer | LATTICE SEMICONDUCTOR |
| Series | LatticeXP2 |
| LFXP2-8E-5QN208C datasheets |
|
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Specifications of LFXP2-8E-5QN208C | |||
|---|---|---|---|
| No. Of Logic Blocks | 8000 | No. Of Macrocells | 4000 |
| Family Type | LatticeXP2 | No. Of Speed Grades | 5 |
| No. Of I/o's | 146 | Clock Management | PLL |
| Total Ram Bits | 221Kbit | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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Lattice Semiconductor
Figure 2-2. PFU Diagram
LUT4 &
LUT4 &
CARRY
CARRY
Slice 0
D
D
FF
FF
Slice
Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3
contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,
a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks
along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be com-
bined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset func-
tions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as posi-
tive/negative edge triggered or level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slice
Resources
Slice 0
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Slice 1
2 LUT4s and 2 Registers
Slice 2
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Slice 3
2 LUT4s
Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja-
cent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has
13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice
2.
From
Routing
LUT4 &
LUT4 &
LUT4 &
CARRY
CARRY
CARRY
Slice 1
Slice 2
D
D
D
FF
FF
FF
To
Routing
PFU BLock
Modes
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, ROM
2-3
Architecture
LatticeXP2 Family Data Sheet
LUT4 &
LUT4
LUT4
CARRY
Slice 3
D
FF
PFF Block
Resources
Modes
Logic, Ripple, ROM
Logic, Ripple, ROM
Logic, Ripple, ROM
2 LUT4s
Logic, ROM
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