IC, LATTICEXP2 FPGA, 435MHZ, QFP-208

 

LFXP2-8E-5QN208C

Manufacturer Part NumberLFXP2-8E-5QN208C
DescriptionIC, LATTICEXP2 FPGA, 435MHZ, QFP-208
ManufacturerLATTICE SEMICONDUCTOR
SeriesLatticeXP2
LFXP2-8E-5QN208C datasheets

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Specifications of LFXP2-8E-5QN208C

No. Of Logic Blocks8000No. Of Macrocells4000
Family TypeLatticeXP2No. Of Speed Grades5
No. Of I/o's146Clock ManagementPLL
Total Ram Bits221KbitLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
Figure 2-3. Slice Diagram
FXB
FXA
A1
B1
C1
D1
M1
M0
From
Routing
A0
B0
C0
D0
CE
CLK
LSR
* Not in Slice 3
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
Table 2-2. Slice Signal Descriptions
Function
Type
Input
Data signal
Input
Data signal
Input
Multi-purpose
Input
Multi-purpose
Input
Control signal
Input
Control signal
Input
Control signal
Input
Inter-PFU signal
Input
Inter-slice signal
Input
Inter-slice signal
Output
Data signals
Output
Data signals
Output
Data signals
Output
Data signals
Output
Inter-PFU signal
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
FCO from Slice/PFU, FCI into Different Slice/PFU
CO
F/SUM
LUT4 &
CARRY*
CI
CO
LUT4 &
CARRY*
F/SUM
CI
FCI into Slice/PFU, FCO from Different Slice/PFU
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
Signal Names
A0, B0, C0, D0
Inputs to LUT4
A1, B1, C1, D1
Inputs to LUT4
M0
Multipurpose Input
M1
Multipurpose Input
CE
Clock Enable
LSR
Local Set/Reset
CLK
System Clock
FCI
Fast Carry-In
FXA
Intermediate signal to generate LUT6 and LUT7
FXB
Intermediate signal to generate LUT6 and LUT7
F0, F1
LUT4 output register bypass signals
Q0, Q1
Register outputs
OFX0
Output of a LUT5 MUX
OFX1
Output of a LUT6, LUT7, LUT8
FCO
Slice 2 of each PFU is the fast carry chain output
2-4
LatticeXP2 Family Data Sheet
SLICE
OFX1
F1
D
Q1
FF*
To
Routing
LUT5
Mux
OFX0
F0
Q0
D
FF*
Description
1
2
MUX depending on the slice
Architecture
1

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