LFXP2-8E-5QN208C | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5QN208C |
| Description | IC, LATTICEXP2 FPGA, 435MHZ, QFP-208 |
| Manufacturer | LATTICE SEMICONDUCTOR |
| Series | LatticeXP2 |
| LFXP2-8E-5QN208C datasheets |
|
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Specifications of LFXP2-8E-5QN208C | |||
|---|---|---|---|
| No. Of Logic Blocks | 8000 | No. Of Macrocells | 4000 |
| Family Type | LatticeXP2 | No. Of Speed Grades | 5 |
| No. Of I/o's | 146 | Clock Management | PLL |
| Total Ram Bits | 221Kbit | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with
DQS Strobe
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Top and Bottom Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits
of data for the left and right edges and up to 18 bits of data for the top and bottom
edges. In some packages, all the potential DDR data (DQ) pins may not be available.
PIC numbering definitions are provided in the “Signal Names” column of the Signal
Descriptions table.
LatticeXP2 Family Data Sheet
DDR Strobe (DQS) and
PIO Within PIC
Data (DQ) Pins
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
[Edge]DQSn
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
[Edge]DQSn
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
A
DQ
B
DQ
4-3
Pinout Information
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