LC4256V-75TN100C LATTICE SEMICONDUCTOR, LC4256V-75TN100C Datasheet - Page 23

• Manufacturer Part Number: LC4256V-75TN100C
• Description: MACH4000 ISP CPLD, 4256, TQFP100
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspMACH 4000r

Specifications of LC4256V-75TN100C

• No. Of Macrocells: 256
• No. Of I/o's: 64
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.5ns
• Frequency: 322MHz
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Parameter
PD
PD_MC
S
ST
SIR
SIRZ
H
HT
HIR
HIRZ
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
GW
WIR
MAX
MAX
4
(Ext.) Clock frequency with external feedback, [1/ (t
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macrocell
GLB register setup time before clock
GLB register setup time before clock with T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
GLB register hold time after clock, input register path with
zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or high (for
high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
Description
Over Recommended Operating Conditions
1, 2, 3
S
+ t
23
CO
)]
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
227
156
3.0
3.2
1.2
2.2
0.0
0.0
1.0
0.0
2.0
2.2
2.2
2.2
—
—
—
—
—
—
—
-5
Max.
5.0
5.5
3.4
6.3
7.0
9.0
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
168
111
4.5
4.7
1.7
2.7
0.0
0.0
1.0
0.0
4.0
3.3
3.3
3.3
—
—
—
—
—
—
—
-75
Max.
10.3
7.5
8.0
4.5
9.0
9.0
7.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
125
5.5
5.5
1.7
2.7
0.0
0.0
1.0
0.0
4.0
4.0
4.0
4.0
86
—
—
—
—
—
—
—
-10
Max.
10.0
10.5
10.5
10.5
12.0
6.0
8.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Timing v.3.2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns