LC4256V-75TN100C LATTICE SEMICONDUCTOR, LC4256V-75TN100C Datasheet - Page 4

• Manufacturer Part Number: LC4256V-75TN100C
• Description: MACH4000 ISP CPLD, 4256, TQFP100
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspMACH 4000r

Specifications of LC4256V-75TN100C

• No. Of Macrocells: 256
• No. Of I/o's: 64
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.5ns
• Frequency: 322MHz
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
from GRP
36 Inputs
4
Generator
Clock
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
Output Enable
Product Term
Sharing
To