LC4256V-75TN100C LATTICE SEMICONDUCTOR, LC4256V-75TN100C Datasheet - Page 42

MACH4000 ISP CPLD, 4256, TQFP100

LC4256V-75TN100C

Manufacturer Part Number
LC4256V-75TN100C
Description
MACH4000 ISP CPLD, 4256, TQFP100
Manufacturer
LATTICE SEMICONDUCTOR
Series
IspMACH 4000r
Datasheet

Specifications of LC4256V-75TN100C

No. Of Macrocells
256
No. Of I/o's
64
Propagation Delay
7.5ns
Global Clock Setup Time
4.5ns
Frequency
322MHz
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Lattice Semiconductor
Signal Descriptions
ispMACH 4000V/B/C ORP Reference Table
ispMACH 4000Z ORP Reference Table
TMS
TCK
TDI
TDO
GOE0/IO, GOE1/IO
GND
NC
V
CLK0/I, CLK1/I, CLK2/I, CLK3/I
V
yzz
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
Number of I/Os
Number of GLBs
Number of I/Os /
GLB
Reference ORP
Table
1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.
2. 64-macrocesll device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.
3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os
4. 256-macrocell device, 144 TQFP: 16 GLBs have 6 I/Os per
5. 512-macrocell device: 20 GLBs have 8 I/Os per, 12 GLBs have 4 I/Os per
Number of I/Os
Number of GLBs
Number of I/Os / GLB
Reference ORP Table
1. 256-macrocell device, 132 csBGA: 16 GLBs have 6 I/Os per
CC
CCO0
, V
CCO1
Signal Names
4032V/B/C
30
16
16 I/Os /
2
1
GLB
32
16
2
16 I/Os /
4032Z
GLB
32
16
2
30
8 I/Os /
4
8
GLB
2
4064V/B/C
32
4
8
16 I/Os /
8 I/Os /
GLB
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
These pins are configured to be either Global Output Enable Input or as general I/O
pins
Ground
Not Connected
The power supply pins for logic core
These pins are configured to be either CLK input or as an input
The power supply pins for each I/O bank
Input/Output
reference (alpha) and z is macrocell reference (numeric). z: 0-15
GLB
32
64
16
4
8
4
4064Z
8 I/Os /
GLB
64
8
8
4128V/B/C
16 I/Os /
GLB
1
ispMACH 4032
ispMACH 4064
ispMACH 4128
ispMACH 4256
ispMACH 4384
ispMACH 4512
64
16
– These are the general purpose I/O used by the logic array. y is GLB
4
92
12 I/Os /
12
8
GLB
3
42
96
12
8
8 I/Os /
4 I/Os /
GLB
GLB
ispMACH 4000V/B/C/Z Family Data Sheet
64
64
16
8
8
4
4128Z
8 I/Os /
GLB
96
16
8
4256V/B/C
12 I/Os /
Description
4
GLB
96
12
8
8 I/Os /
GLB
128
16
8
10 I/Os /
4 I/Os /
GLB
160
GLB
16
10
64
16
4
y: A-P, AX-HX
y: A-P, AX-PX
4384V/B/C
128
16
8 I/Os /
8
GLB
y: A-D
y: A-H
y: A-B
y: A-P
8 I/Os /
4256Z
GLB
192
96
16
16
8
8
1
8 I/Os /
GLB
128
16
8
4512V/B/C
8 I/Os /
GLB
of 8 & 4
128
Mixture
8 I/Os /
4 I/Os /
16
8
GLB
GLB
208
16
5

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