LC4256V-75TN100C LATTICE SEMICONDUCTOR, LC4256V-75TN100C Datasheet - Page 9

MACH4000 ISP CPLD, 4256, TQFP100

LC4256V-75TN100C

Manufacturer Part Number
LC4256V-75TN100C
Description
MACH4000 ISP CPLD, 4256, TQFP100
Manufacturer
LATTICE SEMICONDUCTOR
Series
IspMACH 4000r
Datasheet

Specifications of LC4256V-75TN100C

No. Of Macrocells
256
No. Of I/o's
64
Propagation Delay
7.5ns
Global Clock Setup Time
4.5ns
Frequency
322MHz
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4256V-75TN100C
Manufacturer:
LATTICE
Quantity:
2 940
Part Number:
LC4256V-75TN100C
Manufacturer:
LATTICE32
Quantity:
750
Part Number:
LC4256V-75TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4256V-75TN100C
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
LC4256V-75TN100C
0
Company:
Part Number:
LC4256V-75TN100C
Quantity:
180
Company:
Part Number:
LC4256V-75TN100C
Quantity:
3 600
Lattice Semiconductor
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists
of the following elements:
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
From PTOE
5-PT Fast Path
From Macrocell
Output Routing Multiplexer
OE Routing Multiplexer
9
Available Macrocells
ispMACH 4000V/B/C/Z Family Data Sheet
ORP
Bypass
Multiplexer
OE
Output
To I/O
To I/O
Cell
Cell

Related parts for LC4256V-75TN100C