LCMXO1200C-5TN144C LATTICE SEMICONDUCTOR, LCMXO1200C-5TN144C Datasheet
LCMXO1200C-5TN144C
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LCMXO1200C-5TN144C Summary of contents
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MachXO Family Handbook HB1002 Version 02.5, December 2010 ...
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... MachXO Family Timing Adders ....................................................................................................................... 3-15 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor sysCLOCK PLL Timing .................................................................................................................................... 3-16 Flash Download Time ...................................................................................................................................... 3-17 JTAG Port Timing Specifications ..................................................................................................................... 3-17 Switching Test Conditions................................................................................................................................ 3-19 Pinout Information Signal Descriptions ............................................................................................................................................ 4-1 Pin Information Summary................................................................................................................................... 4-2 Power Supply and NC........................................................................................................................................ 4-3 Power Supply and NC (Cont.)............................................................................................................................ 4-4 LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP ................................................................. 4-5 LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP ...
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... Lattice Semiconductor LOC......................................................................................................................................................... 8-10 Design Considerations and Usage................................................................................................................... 8-10 Banking Rules ......................................................................................................................................... 8-10 Zero Hold Time ....................................................................................................................................... 8-10 Fast Output Path ..................................................................................................................................... 8-10 Dedicated Pins ........................................................................................................................................ 8-10 Differential I/O Implementation................................................................................................................ 8-11 Technical Support Assistance.......................................................................................................................... 8-11 Revision History ............................................................................................................................................... 8-12 Appendix A. HDL Attributes for Synplify VHDL Synplify/Precision RTL Synthesis................................................................................................. 8-13 Verilog Synpilfy ...
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... Software Options.............................................................................................................................................. 12-3 Preference Options ................................................................................................................................. 12-3 Configuring SRAM or Programming Flash.............................................................................................. 12-4 Technical Support Assistance.......................................................................................................................... 12-4 Revision History ............................................................................................................................................... 12-5 HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs Introduction ...................................................................................................................................................... 13-1 General Coding Styles for FPGA ..................................................................................................................... 13-1 Hierarchical Coding................................................................................................................................. 13-1 Design Partitioning .................................................................................................................................. 13-2 and GND if Separate Pins are Available ...
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... Coding Styles for FSM ............................................................................................................................ 13-5 Using Pipelines in the Designs................................................................................................................ 13-6 Comparing IF statement and CASE statement ....................................................................................... 13-7 Avoiding Non-intentional Latches............................................................................................................ 13-8 HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 13-8 Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 13-8 Implementing Multiplexers .................................................................................................................... 13-10 Clock Dividers ....................................................................................................................................... 13-10 Register Control Signals ....................................................................................................................... 13-12 Use PIC Features ...
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Section I. MachXO Family Data Sheet DS1002 Version 02.9, July 2010 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex- ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high- security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. ® ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Figure 2-1. Top View of the MachXO1200 Device sysMEM Embedded Block RAM (EBR) sysCLOCK PLL JTAG Port 1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure 2-2. Top View of the MachXO640 Device ...
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... Lattice Semiconductor Figure 2-3. Top View of the MachXO256 Device JTAG Port Programmable Function Units with RAM (PFUs) PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions ...
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... Lattice Semiconductor There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig- nals associated with each Slice. Figure 2-5. Slice Diagram ...
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... Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes PFU Slice ...
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... Lattice Semiconductor Figure 2-6. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK ROM16x1 AD0 AD1 AD2 AD3 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. ...
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... Lattice Semiconductor The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control Distribution Network The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks ...
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... Lattice Semiconductor Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices Routing Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. Figure 2-9. Secondary Clocks for MachXO Devices ...
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... Lattice Semiconductor sysCLOCK Phase Locked Loops (PLLs) The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin) ...
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... Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing I PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKFB CLKINTFB port RST I “1” to reset the input clock divider CLKOS ...
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... Lattice Semiconductor Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port ...
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... Lattice Semiconductor The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. ...
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... Lattice Semiconductor Figure 2-13. Memory Core Reset RSTA RSTB GSRN For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14 ...
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... Lattice Semiconductor PIO Groups On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO groups with six IOs are placed on the top and bottom ...
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... Lattice Semiconductor output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 shows the MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their complements. In addition a global signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer. ...
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... Lattice Semiconductor of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after V CC figured. The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer ...
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... Lattice Semiconductor Table 2-8. I/O Support Device by Device MachXO256 Number of I/O Banks 2 Single-ended (all I/O Banks) Type of Input Buffers Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers Differential Output All I/O Banks Emulation Capability PCI Support No Table 2-9 ...
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... Lattice Semiconductor Table 2-10. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain 3 PCI33 Differential Interfaces 1, 2 LVDS 2 BLVDS, RSDS 2 LVPECL 1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers. ...
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... Lattice Semiconductor Figure 2-18. MachXO2280 Banks V CCIO7 GND V CCIO6 GND Figure 2-19. MachXO1200 Banks V CCIO7 GND V CCIO6 GND Bank 0 Bank Bank 5 Bank Bank 0 Bank Bank 5 Bank 2-19 Architecture MachXO Family Data Sheet V CCIO2 GND V CCIO3 GND V CCIO2 GND V CCIO3 GND ...
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... Lattice Semiconductor Figure 2-20. MachXO640 Banks V CCO3 GND Figure 2-21. MachXO256 Banks GND V CCO1 Hot Socketing The MachXO devices have been carefully designed to ensure predictable behavior during power-up and power- down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of ...
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... Lattice Semiconductor the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applica- tions. Sleep Mode The MachXO “C” devices (V = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dra- CC matically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. ...
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... Lattice Semiconductor Device Configuration All MachXO devices contain a test access port that can be used for device configuration and programming. The non-volatile memory in the MachXO can be configured in two different modes: • In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by BSCAN registers. • ...
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... Lattice Semiconductor Figure 2-22. MachXO Configuration and Programming Port Background Mode Program in seconds Non-Volatile Memory Space Density Shifting The MachXO family has been designed to enable density migration in the same package. Furthermore, the archi- tecture ensures a high success rate when performing design migration from lower density parts to higher density parts ...
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... PU © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com MachXO Family Data Sheet ...
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... Lattice Semiconductor MachXO1200 and MachXO2280 Hot Socketing Specifications Symbol Parameter Non-LVDS General Purpose sysIOs I Input or I/O Leakage Current DK LVDS General Purpose sysIOs I Input or I/O Leakage Current DK_LVDS 1. Insensitive to sequence CC, CCAUX, (MAX CCIO CCIO additive PU LVCMOS and LVTTL only. ...
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... Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C 4 All LCMXO ‘C’ Devices Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices 3-3 DC and Switching Characteristics MachXO Family Data Sheet 3 Typ ...
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... Frequency = 0MHz. 4. Typical user pattern power supplies at nominal voltage Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Over Recommended Operating Conditions Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C LCMXO640E/C LCMXO1200E/C LCMXO2280E/C 6 All devices or GND. 3-4 DC and Switching Characteristics ...
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... Assumes all I/O pins are held at V CCIO 3. Typical user pattern. 4. JTAG programming is at 25MHz 25°C, power supplies at nominal voltage Per Bank 2.5V. Does not include pull-up/pull-down. CCIO Device LCMXO256C LCMXO640C LCMXO1200C LCMXO2280C LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256C/E LCMXO640C/E LCMXO1200/E LCMXO2280C/E 6 All devices or GND. ...
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... Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL 3 PCI 1, 2 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers 3 ...
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... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.42 (“C” Version) LVCMOS 1.2 -0 ...
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... Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input Voltage INP, INM V Differential Input Threshold THD V Input Common Mode Voltage CM I Input current IN V Output high voltage for Output low voltage for Output voltage differential OD Change in V between high and ...
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... Lattice Semiconductor Table 3-1. LVDS DC Conditions Parameter Z Output impedance OUT R Driver series resistor S R Driver parallel resistor P R Receiver termination T V Output high voltage OH V Output low voltage OL V Output differential voltage OD V Output common mode voltage CM Z Back impedance BACK ...
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... Lattice Semiconductor Table 3-2. BLVDS DC Conditions Symbol Z OUT R TLEFT R TRIGHT For input buffer, see LVDS table. LVPECL The MachXO family supports the differential LVPECL standard through emulation. This output standard is emu- lated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices ...
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... Lattice Semiconductor For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. RSDS The MachXO family supports the differential RSDS standard. The output standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer on certain devices ...
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... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions (1200 and 2280 Devices Only) ...
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... Lattice Semiconductor MachXO External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Global Clock without PLL) t Best Case t Through 1 LUT Best Case Clock to Output - From PFU CO t Clock to Data Setup - To PFU SU t Clock to Data Hold - To PFU H f Clock Frequency of I/O and PFU Register ...
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... Lattice Semiconductor MachXO Internal Timing Parameters Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU LSR_PFU t Clock to Mux (M0,M1) input setup time SUM_PFU t Clock to Mux (M0,M1) input hold time ...
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... Lattice Semiconductor MachXO Family Timing Adders Buffer Type Input Adjusters 4 LVDS25 LVDS 4 BLVDS25 BLVDS 4 LVPECL33 LVPECL LVTTL33 LVTTL LVCMOS33 LVCMOS 3.3 LVCMOS25 LVCMOS 2.5 LVCMOS18 LVCMOS 1.8 LVCMOS15 LVCMOS 1.5 LVCMOS12 LVCMOS 1.2 4 PCI33 PCI Output Adjusters LVDS25E LVDS 2 LVDS25 LVDS 2.5 BLVDS25 BLVDS 2 ...
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... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter ...
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... Lattice Semiconductor I/O SLEEPN Flash Download Time Symbol Minimum CCAUX t (later of the two supplies) REFRESH to Device I/O Active JTAG Port Timing Specifications Symbol f TCK [BSCAN] clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH ...
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... Lattice Semiconductor Figure 3-5. JTAG Port Timing Waveforms TMS TDI TCK TDO Data to be captured from I/O Data to be driven out to I BTS BTH t t BTCPL BTCPH t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN 3-18 DC and Switching Characteristics MachXO Family Data Sheet ...
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... Lattice Semiconductor Switching Test Conditions Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and LVCMOS settings (L -> ...
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... Applies to MachXO “C” devices only. NC for “E” devices. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... These devices support on-chip LVDS buffers for left and right I/O Banks. LCMXO256C/E 100 csBGA 100 TQFP — — 2 — — 41/20 41/20 18/5 37/18 37/18 21/4 — — 14/2 — — 21/6 LCMXO1200C/E 256 caBGA / 144 TQFP 132 csBGA 256 ftBGA 113 101 211 48 42 105 ...
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... Lattice Semiconductor Power Supply and NC Signal 100 TQFP VCC LCMXO256/640: 35, 90 LCMXO1200/2280: 17, 35, 66, 91 VCCIO0 LCMXO256: 60, 74, 92 LCMXO640: 80, 92 LCMXO1200/2280: 94 VCCIO1 LCMXO256: 10, 24, 41 LCMXO640: 60, 74 LCMXO1200/2280: 80 VCCIO2 LCMXO256: None LCMXO640: 29, 41 LCMXO1200/2280: 70 VCCIO3 LCMXO256: None LCMXO640: 10, 24 LCMXO1200/2280: 56 VCCIO4 LCMXO256/640: None ...
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... Lattice Semiconductor Power Supply and NC (Cont.) Signal 132 csBGA VCC H3, P6, G12, C7 VCCIO0 LCMXO640: B11, C5 LCMXO1200/2280: C5 VCCIO1 LCMXO640: L12, E12 LCMXO1200/2280: B11 VCCIO2 LCMXO640: N2, M10 LCMXO1200/2280: E12 LCMXO640: D2, K3 VCCIO3 LCMXO1200/2280: L12 VCCIO4 LCMXO640: None LCMXO1200/2280: M10 VCCIO5 LCMXO640: None ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP LCMXO256 Ball Pin Number Function Bank 1 PL2A 1 2 PL2B 1 3 PL3A 1 4 PL3B 1 5 PL3C 1 6 PL3D 1 7 PL4A 1 8 PL4B 1 9 PL5A 1 10 VCCIO1 1 11 PL5B 1 12 GNDIO1 1 13 PL5C ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Ball Pin Number Function Bank 43 PB4A 1 44 PB4B 1 45 PB4C 1 46 PB4D 1 47 PB5A 1 48* SLEEPN - 49 PB5C 1 50 PB5D 1 51 PR9B 0 52 PR9A 0 53 PR8B 0 54 PR8A 0 55 PR7D ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.) LCMXO256 Ball Pin Number Function Bank 85 PT4B 0 86 PT4A 0 87 PT3D 0 88 VCCAUX - 89 PT3C 0 90 VCC - 91 PT3B 0 92 VCCIO0 0 93 GNDIO0 0 94 PT3A 0 95 PT2F 0 96 PT2E 0 97 PT2D 0 98 ...
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... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP LCMXO1200 Pin Ball Number Function Bank 1 PL2A 7 2 PL2B 7 3 PL3C 7 4 PL3D 7 5 PL4B 7 6 VCCIO7 7 7 PL6A 7 8 PL6B 7 9 GND - 10 PL7C 7 11 PL7D 7 12 PL8C 7 13 PL8D 7 14 ...
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... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Ball Number Function Bank 42 PB9A 4 43 PB9B 4 44 VCCIO4 4 45 PB10A 4 46 PB10B 4 47*** SLEEPN - 48 PB11A 4 49 PB11B 4 GNDIO3 50** - GNDIO4 51 PR16B 3 52 PR15B 3 53 PR15A 3 54 PR14B 3 55 ...
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... Lattice Semiconductor LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.) LCMXO1200 Pin Ball Number Function Bank 82 PT9A 1 83 GND - 84 PT8B 1 85 PT8A 1 86 PT7D 1 87 PT6F 0 88 PT6D 0 89 PT6C 0 90 VCCAUX - 91 VCC - 92 PT5B 0 93 PT4B 0 94 VCCIO0 0 95 PT3D ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA LCMXO256 Ball Ball Number Function Bank B1 PL2A 1 C1 PL2B 1 D2 PL3A 1 D1 PL3B 1 C2 PL3C 1 E1 PL3D 1 E2 PL4A 1 F1 PL4B 1 F2 PL5A 1 G2 PL5B 1 H1 GNDIO1 1 H2 PL5C 1 J1 PL5D ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Ball Number Function Bank P13 PB5A 1 M12* SLEEPN - P14 PB5C 1 N13 PB5D 1 N14 PR9B 0 M14 PR9A 0 L13 PR8B 0 L14 PR8A 0 M13 PR7D 0 K14 PR7C 0 K13 PR7B 0 J14 PR7A ...
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... Lattice Semiconductor LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.) LCMXO256 Ball Ball Number Function Bank A4 GNDIO0 0 B4 PT3A 0 A3 PT2F 0 B3 PT2E 0 A2 PT2D 0 C3 PT2C 0 A1 PT2B 0 B2 PT2A 0 N9 GND - B9 GND - B5 VCCIO0 0 A14 VCCIO0 0 H14 VCCIO0 0 P10 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # B1 PL2A PL2B PL2C PL2D PL3A PL3B PL3D 3 E1 GNDIO3 3 E2 PL5A PL5B 3 GSRN C F2 PL5D 3 F3 PL6B 3 G1 PL6C PL6D ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA (Cont.) LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # M9 PB7B 2 C N10 PB7E 2 T P10 PB7F 2 C N11 GNDIO2 2 P11 PB8C 2 T M11 PB8D 2 C P12 PB9C 2 T P13 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA (Cont.) LCMXO640 Ball Dual Ball # Function Bank Function Differential Ball # B9 PT7B PT7A PT6B 0 PCLK0_1*** C B8 PT6A PT5B 0 PCLK0_0*** C B7 PT5A VCCAUX - C7 VCC - A6 PT4D PT4C PT3F PT3E PT3D 0 B4 GNDIO0 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP LCMXO640 Pin Ball Dual Number Function Bank Function Differential 1 PL2A 3 2 PL2C 3 3 PL2B 3 4 PL3A 3 5 PL2D 3 6 PL3B 3 7 PL3C 3 8 PL3D 3 9 PL4A 3 10 VCCIO3 3 11 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP (Cont.) LCMXO640 Pin Ball Dual Number Function Bank Function Differential 51 TDI 2 TDI 52 VCC - 53 VCCAUX - 54 PB5A 2 55 PB5B 2 PCLKT2_1*** 56 PB5D 2 57 PB6A 2 58 PB6B 2 PCLKT2_0*** 59 GND - 60 PB7C 2 61 PB7E 2 62 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP (Cont.) LCMXO640 Pin Ball Dual Number Function Bank Function Differential 101 PR3D 1 102 PR3C 1 103 PR3B 1 104 PR2D 1 105 PR3A 1 106 PR2B 1 107 PR2C 1 108 PR2A 1 109 PT9F 0 110 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA LCMXO640 Ball Ball Dual Number Function Bank Function Differential GND GNDIO3 3 VCCIO3 VCCIO3 PL3A PL3B PL2C PL2D PL2A PL2B 3 C VCCIO3 VCCIO3 3 GND GNDIO3 3 D2 PL3C PL3D ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential J4 PL8A PL8B PL11A PL11B PL10C PL10D PL11C PL11D 3 C VCCIO3 VCCIO3 3 GND GNDIO3 3 GND GNDIO2 2 VCCIO2 VCCIO2 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential - - - - M10 PB6A PB6C 2 T R10 PB6D 2 C T10 PB7C 2 T T11 PB7D 2 C N10 NC N11 NC VCCIO2 VCCIO2 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential J13 PR8C 1 T GND GND - K14 PR8B 1 C J14 PR8A 1 T K15 PR7D 1 C J15 PR7C K12 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential E11 NC E10 NC D12 PT9D 0 C D11 PT9C 0 T A14 PT7F 0 C A13 PT7E 0 T C12 PT8B 0 C C11 ...
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... Lattice Semiconductor LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA (Cont.) LCMXO640 Ball Ball Dual Number Function Bank Function Differential PT2B PT2A VCCIO0 VCCIO0 0 GND GNDIO0 0 A1 GND - A16 GND - F11 GND - G8 GND - G9 GND - H7 GND - H8 GND - H9 GND ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA Ball Number Ball Function GND GNDIO7 VCCIO7 VCCIO7 D4 PL2A F5 PL2B B3 PL3A C3 PL3B E4 PL3C G6 PL3D A1 PL4A B1 PL4B F4 PL4C VCC VCC E3 PL4D D2 PL5A D3 PL5B G5 PL5C F3 PL5D C2 PL6A VCCIO7 VCCIO7 GND GNDIO7 C1 PL6B H5 PL6C G4 PL6D E2 PL7A ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G2 PL11A H2 PL11B L3 PL11C L5 PL11D H1 PL12A VCCIO6 VCCIO6 GND GNDIO6 J2 PL12B L4 PL12C L6 PL12D K2 PL13A K1 PL13B J1 PL13C VCC VCC L2 PL13D M5 PL14D M3 PL14C L1 PL14B M2 PL14A M1 PL15A N1 PL15B M6 PL15C M4 PL15D VCCIO6 VCCIO6 ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function T2 PL20B P6 TMS V1 PB2A U2 PB2B T3 PB2C N7 TCK R4 PB2D R5 PB3A T4 PB3B VCC VCC R6 PB3C P7 PB3D U3 PB4A T5 PB4B V2 PB4C N8 TDO V3 PB4D T6 PB5A GND GNDIO5 VCCIO5 VCCIO5 U4 PB5B P8 PB5C T7 PB5D V4 TDI R8 PB6A ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function V10 PB9B N10 PB9C R10 PB9D P10 PB10F T10 PB10E U10 PB10D V11 PB10C U11 PB10B VCCIO4 VCCIO4 GND GNDIO4 T11 PB10A U12 PB11A R11 PB11B GND GND ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function GND GNDIO3 VCCIO3 VCCIO3 P15 PR20B N14 PR20A N15 PR19B M13 PR19A R15 PR18B T16 PR18A N16 PR17D M14 PR17C U17 PR17B VCC VCC U18 PR17A R17 PR16D ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function J13 PR10C M18 PR10B L18 PR10A GND GNDIO2 VCCIO2 VCCIO2 H16 PR9D H14 PR9C K18 PR9B J18 PR9A J17 PR8D VCC VCC H18 PR8C H17 PR8B G17 PR8A ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function E13 PT16D C15 PT16C F13 PT16B D14 PT16A A18 PT15D B17 PT15C A16 PT15B A17 PT15A VCC VCC D13 PT14D F12 PT14C C14 PT14B E12 PT14A C13 PT13D ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function A10 PT8E VCCIO0 VCCIO0 GND GNDIO0 A9 PT8D C9 PT8C B9 PT8B F9 VCCAUX A8 PT8A B8 PT7D C8 PT7C VCC VCC A7 PT7B B7 PT7A A6 PT6A B6 PT6B D8 PT6C F8 PT6D C7 PT6E E8 PT6F D7 PT5D VCCIO0 VCCIO0 GND GNDIO0 ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function F16 GND H10 GND H11 GND H8 GND H9 GND J10 GND J11 GND J4 GND J8 GND J9 GND K10 GND K11 GND K17 GND K8 GND K9 GND L10 GND L11 GND L8 GND ...
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... Lattice Semiconductor LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.) Ball Number Ball Function G8 VCCIO0 G7 VCCIO0 * Supports true LVDS outputs for “E” devices. *** Primary clock inputs are single-ended. MachXO Family Data Sheet LCMXO2280 Bank Dual Function 0 0 4-35 Pinout Information Differential ...
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... Lattice Semiconductor Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits ...
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... The markings appears as follows: © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Part Number LUTs LCMXO1200C-3T100C 1200 LCMXO1200C-4T100C 1200 LCMXO1200C-5T100C 1200 LCMXO1200C-3T144C 1200 LCMXO1200C-4T144C 1200 LCMXO1200C-5T144C 1200 LCMXO1200C-3M132C 1200 LCMXO1200C-4M132C 1200 LCMXO1200C-5M132C 1200 LCMXO1200C-3B256C 1200 LCMXO1200C-4B256C 1200 LCMXO1200C-5B256C 1200 LCMXO1200C-3FT256C 1200 LCMXO1200C-4FT256C 1200 LCMXO1200C-5FT256C 1200 Commercial Supply Voltage I/Os Grade 1.8V/2.5V/3.3V 78 1.8V/2.5V/3.3V 78 1.8V/2.5V/3.3V 78 1.8V/2.5V/3. ...
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... Lattice Semiconductor Part Number LUTs LCMXO2280C-3T100C 2280 LCMXO2280C-4T100C 2280 LCMXO2280C-5T100C 2280 LCMXO2280C-3T144C 2280 LCMXO2280C-4T144C 2280 LCMXO2280C-5T144C 2280 LCMXO2280C-3M132C 2280 LCMXO2280C-4M132C 2280 LCMXO2280C-5M132C 2280 LCMXO2280C-3B256C 2280 LCMXO2280C-4B256C 2280 LCMXO2280C-5B256C 2280 LCMXO2280C-3FT256C 2280 LCMXO2280C-4FT256C 2280 LCMXO2280C-5FT256C 2280 LCMXO2280C-3FT324C 2280 LCMXO2280C-4FT324C 2280 LCMXO2280C-5FT324C 2280 ...
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... Lattice Semiconductor Part Number LUTs LCMXO1200E-3T100C 1200 LCMXO1200E-4T100C 1200 LCMXO1200E-5T100C 1200 LCMXO1200E-3T144C 1200 LCMXO1200E-4T144C 1200 LCMXO1200E-5T144C 1200 LCMXO1200E-3M132C 1200 LCMXO1200E-4M132C 1200 LCMXO1200E-5M132C 1200 LCMXO1200E-3B256C 1200 LCMXO1200E-4B256C 1200 LCMXO1200E-5B256C 1200 LCMXO1200E-3FT256C 1200 LCMXO1200E-4FT256C 1200 LCMXO1200E-5FT256C 1200 Part Number LUTs LCMXO2280E-3T100C 2280 LCMXO2280E-4T100C ...
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... LCMXO640C-3FT256I 640 LCMXO640C-4FT256I 640 Part Number LUTs LCMXO1200C-3T100I 1200 LCMXO1200C-4T100I 1200 LCMXO1200C-3T144I 1200 LCMXO1200C-4T144I 1200 LCMXO1200C-3M132I 1200 LCMXO1200C-4M132I 1200 LCMXO1200C-3B256I 1200 LCMXO1200C-4B256I 1200 LCMXO1200C-3FT256I 1200 LCMXO1200C-4FT256I 1200 Part Number LUTs LCMXO2280C-3T100I 2280 LCMXO2280C-4T100I 2280 LCMXO2280C-3T144I 2280 LCMXO2280C-4T144I 2280 LCMXO2280C-3M132I 2280 ...
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... Lattice Semiconductor Part Number LUTs LCMXO256E-3T100I 256 LCMXO256E-4T100I 256 LCMXO256E-3M100I 256 LCMXO256E-4M100I 256 Part Number LUTs LCMXO640E-3T100I 640 LCMXO640E-4T100I 640 LCMXO640E-3M100I 640 LCMXO640E-4M100I 640 LCMXO640E-3T144I 640 LCMXO640E-4T144I 640 LCMXO640E-3M132I 640 LCMXO640E-4M132I 640 LCMXO640E-3B256I 640 LCMXO640E-4B256I 640 LCMXO640E-3FT256I 640 LCMXO640E-4FT256I 640 Part Number ...
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... LCMXO640C-5BN256C 640 LCMXO640C-3FTN256C 640 LCMXO640C-4FTN256C 640 LCMXO640C-5FTN256C 640 Part Number LUTs LCMXO1200C-3TN100C 1200 LCMXO1200C-4TN100C 1200 LCMXO1200C-5TN100C 1200 LCMXO1200C-3TN144C 1200 LCMXO1200C-4TN144C 1200 LCMXO1200C-5TN144C 1200 LCMXO1200C-3MN132C 1200 LCMXO1200C-4MN132C 1200 LCMXO1200C-5MN132C 1200 LCMXO1200C-3BN256C 1200 LCMXO1200C-4BN256C 1200 LCMXO1200C-5BN256C 1200 LCMXO1200C-3FTN256C 1200 LCMXO1200C-4FTN256C 1200 LCMXO1200C-5FTN256C 1200 ...
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... Lattice Semiconductor Part Number LUTs LCMXO2280C-3TN100C 2280 LCMXO2280C-4TN100C 2280 LCMXO2280C-5TN100C 2280 LCMXO2280C-3TN144C 2280 LCMXO2280C-4TN144C 2280 LCMXO2280C-5TN144C 2280 LCMXO2280C-3MN132C 2280 LCMXO2280C-4MN132C 2280 LCMXO2280C-5MN132C 2280 LCMXO2280C-3BN256C 2280 LCMXO2280C-4BN256C 2280 LCMXO2280C-5BN256C 2280 LCMXO2280C-3FTN256C 2280 LCMXO2280C-4FTN256C 2280 LCMXO2280C-5FTN256C 2280 LCMXO2280C-3FTN324C 2280 LCMXO2280C-4FTN324C 2280 LCMXO2280C-5FTN324C 2280 ...
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... Lattice Semiconductor Part Number LUTs LCMXO1200E-3TN100C 1200 LCMXO1200E-4TN100C 1200 LCMXO1200E-5TN100C 1200 LCMXO1200E-3TN144C 1200 LCMXO1200E-4TN144C 1200 LCMXO1200E-5TN144C 1200 LCMXO1200E-3MN132C 1200 LCMXO1200E-4MN132C 1200 LCMXO1200E-5MN132C 1200 LCMXO1200E-3BN256C 1200 LCMXO1200E-4BN256C 1200 LCMXO1200E-5BN256C 1200 LCMXO1200E-3FTN256C 1200 LCMXO1200E-4FTN256C 1200 LCMXO1200E-5FTN256C 1200 Part Number LUTs LCMXO2280E-3TN100C 2280 LCMXO2280E-4TN100C ...
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... LCMXO640C-3FTN256I 640 LCMXO640C-4FTN256I 640 Part Number LUTs LCMXO1200C-3TN100I 1200 LCMXO1200C-4TN100I 1200 LCMXO1200C-3TN144I 1200 LCMXO1200C-4TN144I 1200 LCMXO1200C-3MN132I 1200 LCMXO1200C-4MN132I 1200 LCMXO1200C-3BN256I 1200 LCMXO1200C-4BN256I 1200 LCMXO1200C-3FTN256I 1200 LCMXO1200C-4FTN256I 1200 Part Number LUTs LCMXO2280C-3TN100I 2280 LCMXO2280C-4TN100I 2280 LCMXO2280C-3TN144I 2280 LCMXO2280C-4TN144I 2280 LCMXO2280C-3MN132I 2280 ...
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... Lattice Semiconductor Part Number LUTs LCMXO256E-3TN100I 256 LCMXO256E-4TN100I 256 LCMXO256E-3MN100I 256 LCMXO256E-4MN100I 256 Part Number LUTs LCMXO640E-3TN100I 640 LCMXO640E-4TN100I 640 LCMXO640E-3MN100I 640 LCMXO640E-4MN100I 640 LCMXO640E-3TN144I 640 LCMXO640E-4TN144I 640 LCMXO640E-3MN132I 640 LCMXO640E-4MN132I 640 LCMXO640E-3BN256I 640 LCMXO640E-4BN256I 640 LCMXO640E-3FTN256I 640 LCMXO640E-4FTN256I 640 Part Number ...
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... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Architecture © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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... Lattice Semiconductor Date Version April 2006 02.0 Architecture (cont.) (cont.) DC and Switching Characteristics Pinout Information Ordering Information May 2006 02.1 Pinout Information August 2006 02.2 Section “Top View of the MachXO1200 Device” figure updated. (cont.) “Top View of the MachXO640 Device” figure updated. ...
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... Lattice Semiconductor Date Version November 2006 02.3 DC and Switching Characteristics December 2006 02.4 Architecture Pinout Information February 2007 02.5 Architecture August 2007 02.6 DC and Switching Characteristics November 2007 02.7 DC and Switching Characteristics Pinout Information Supplemental Information June 2009 02.8 Introduction Pinout Information ...
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Section II. MachXO Family Technical Notes ...
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... Input on the top bank of the MachXO1200 and MachXO2280 only. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor sysIO Banking Scheme The MachXO family has a non-homogeneous I/O banking structure. The MachXO256 has two I/O banks, the MachXO640 has four I/O banks and the two largest devices, the MachXO1200 and the MachXO2280, have eight I/O banks. The figures below show the banking structures in each of the devices. Each sysIO bank has a V supply voltage ...
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... Lattice Semiconductor Figure 8-2. MachXO640 sysIO Banking V CCO3 GND Figure 8-3. MachXO1200 and MachXO2280 sysIO Banking V CCIO7 GND V CCIO6 GND 1 N Bank Bank Bank 0 Bank Bank 5 Bank 8-3 MachXO sysIO Usage Guide V CCO1 GND V CCIO2 GND V CCIO3 GND ...
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... Lattice Semiconductor V (1.2V/1.5V/1.8V/2.5V/3.3V) CCIO Each bank has a separate V CCIO such as LVTTL, LVCMOS and PCI. LVTTL, LVCMOS3.3, LVCMOS2.5 and LVCMOS1.2 also have fixed threshold options allowing them to be placed in any bank and is independent of bank V bank determines the ratioed input standards that can be supported in that bank also used to power the differ- ential output drivers ...
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... Lattice Semiconductor sysIO Standards Supported in Each Bank Table 8-3. I/O Standards Supported by Various Banks in the MachXO640 and MachXO256 Description Bank 0 I/O Buffer Type Single-ended LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 Output Standards LVCMOS12 Supported 1 LVDS25E 1 LVPECL 1 BLVDS 1 RSDS Inputs All Single-ended Clock Inputs All Single-ended 1 ...
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... Lattice Semiconductor Programmable Drive All LVCMOS and LVTTL single-ended drivers have programmable drive strength. This option can be set for each I/O independently. The table below lists the programmable drive strengths available for each I/O standard. The actual value will vary with the I/O voltage. The user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength ...
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... Lattice Semiconductor Figure 8-4. 5V Input Interface Example 5V Input The value of this external resistor will depend on the PCI clamp diode characteristics. The voltage vs. current data across this diode can be found in the device IBIS model. In order to interface to 5V input recommended that the V Below is an example of how to calculate the value of this external resistor when V • ...
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... Lattice Semiconductor If the V of the bank is increased, it will also increase the value of the external resistor required. Keep in mind CCIO that changing the Bank V will change the value of the input threshold voltage. CCIO Software sysIO Attributes sysIO attributes can be specified in the HDL, using the Preference Editor GUI in ispLEVER in Lattice Diamond™ ...
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... Lattice Semiconductor OPENDRAIN LVCMOS and LVTTL I/O standards can be set to open-drain configuration by using the OPENDRAIN attribute. Values: ON, OFF Default: OFF DRIVE The Drive Strength attribute is available for LVTTL and LVCMOS output standards. These can be set or each I/O pin individually. The programmable drive available on a pad will depend on the V strength available for different I/O standards and the defaults for each of them ...
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... Lattice Semiconductor SLEWRATE The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual slew rate control. This allows designers to specify the slew rate control on pin-by-pin basis. Values: FAST, SLOW Default: FAST LOC This attribute can be used to make pin assignments to the I/O ports in the design. This attributes is only used when the pin assignments are made in HDL source ...
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... Lattice Semiconductor Tristate All (TSALLPAD) All MachXO devices have a dedicated TSALLPAD pin that is used to enable or disable the tristate control to all the output buffers. By default, the pin will function as an I/O unless programmed TSALLPAD. This signal also has programmable global polarity control. By default, the polarity is active high. This global tristate control signal can also be generated using user logic ...
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... Lattice Semiconductor Revision History Date — July 2007 September 2010 Version — Previous Lattice releases. 01.4 Correction in VCCIO (1.2V/1.5V/1.8V/2.5V3.3V) text section. VCCIO of Bank2 is used to power the JTAG pin for MachXO640, rather than Bank3. 01.5 Updated for Lattice Diamond design software support. ...
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... Lattice Semiconductor Appendix A. HDL Attributes for Synplify Using these HDL attributes, you can assign the sysIO attributes directly in your source. You will need to use the attribute definition and syntax for the synthesis vendor you are planning to you to use. Below are a list of all the sysIO attributes syntax and examples for Precision RTL Synthesis and Synplify ...
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... Lattice Semiconductor DRIVE --***Attribute Declaration*** ATTRIBUTE DRIVE: string; --***DRIVE assignment for I/O Pin*** ATTRIBUTE DRIVE OF portB: SIGNAL IS “16”; PULLMODE --***Attribute Declaration*** ATTRIBUTE PULLMODE : string; --***PULLMODE assignment for I/O Pin*** ATTRIBUTE PULLMODE OF portA: ATTRIBUTE PULLMODE OF portB: PCICLAMP --***Attribute Declaration*** ATTRIBUTE PCICLAMP: string; ...
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... Lattice Semiconductor Verilog Synpilfy This section lists syntax and examples for all the sysIO attributes in Verilog using the Synplify synthesis tool. Syntax Table 8-12. Verilog Synplify Attribute Syntax Attribute IO_TYPE PinType PinName /* synthesis IO_TYPE=“IO_Type Value”*/; OPENDRAIN PinType PinName /* synthesis OPENDRAIN =“OpenDrain Value”*/; ...
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... Lattice Semiconductor Verilog Precision RTL Synthesis This section lists syntax and examples for all the sysIO attributes in Verilog using the Precision RTL Synthesis syn- thesis tool. Syntax Table 8-13. Verilog Precision RTL Synthesis Attribute Syntax Attribute IO_TYPE OPENDRAIN DRIVE PULLMODE PCICLAMP ...
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... Lattice Semiconductor Appendix B. sysIO Attributes Using the ispLEVER Preference Editor or Diamond Spreadsheet View You can assign the sysIO buffer attributes using the Pre-map Preference Editor GUI available in the ispLEVER or the Spreadsheet View GUI in Diamond. The Pin Attribute sheet in ispLEVER and Port Assignments sheet in Dia- mond list all the ports in your design and all the available sysIO attributes as preferences ...
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... Lattice Semiconductor Figure 8-6. Port Assignment Tab MachXO sysIO Usage Guide 8-18 ...
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... Lattice Semiconductor Appendix C. sysIO Attributes Using Preference File (ASCII File) You can also enter the sysIO Attributes directly in the preference (.prf) file as sysIO buffer preferences. The PRF file is an ASCII file containing two separate sections: a schematic section for those preferences created by the Mapper or Translator, and a user section for preferences entered by the user ...
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... Lattice Semiconductor Example This command places the port Clk0 on the site A4: LOCATE COMP “Clk0” SITE “A4”; This command places the component PFU1 on the site named R1C7: LOCATE COMP “PFU1” SITE “R1C7”; This command places bus1 on ROW 3 and bus2 on COL4 LOCATE BUS “ ...
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... Block RAM (EBR) JTAG Port © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor The PFU contains the building blocks for logic and Distributed RAM and ROM. The PFF provides the logic building blocks without the distributed RAM This document describes the memory usage and implementation for both Embedded Memory Blocks (EBRs) and Distributed RAM of the PFU. Refer to the details on the hardware implementation of the EBR and Distributed RAM ...
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... Lattice Semiconductor Figure 9-2. IPexpress Main Window, ispLEVER Figure 9-3. IPexpress Main Window, Diamond Memory Usage Guide for MachXO Devices 9-3 ...
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... Lattice Semiconductor The left pane of this window includes the Module Tree. The EBR-based Memory Modules are under the EBR_Components and the PFU-based Distributed Memory Modules are under Storage_Components as shown in Figure 9-2 and Figure 9- example, let us consider generating an EBR-based Pseudo Dual Port RAM of size 512x16. Select RAM_DP under the EBR_Components ...
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... Lattice Semiconductor Figure 9-5. Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress in Diamond In this right pane, options like the Device Family, Macro Type, Category, and Module_Name are device and selected module dependent. These cannot be changed in IPexpress. Users can change the directory where the generated module files will be placed by clicking the Browse button in the Project Path ...
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... Lattice Semiconductor Figure 9-6. Generating Pseudo Dual Port RAM (RAM_DP) Module Customization in ispLEVER Figure 9-7. Generating Pseudo Dual Port RAM (RAM_DP) Module Customization in Diamond The left side of this window shows the block diagram of the module. The right side includes the Configuration tab where users can choose options to customize the RAM_DP such as (e ...
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... Lattice Semiconductor The Input Data and the Address Control is always registered, as the hardware only supports the clocked write operation for the EBR based RAMs. The check box Enable Output Registers, inserts the output registers in the Read Data Port, as the output registers are optional for the EBR-based RAMs. ...
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... Lattice Semiconductor The various ports and their definitions for the Single Port Memory are listed in Table 9-1. The table lists the corre- sponding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive. Table 9-1. EBR-based Single Port Memory Port Definitions ...
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... Lattice Semiconductor Table 9-3. Single Port RAM Attributes for MachXO Attribute Description DATA_WIDTH Data Word Width REGMODE Register Mode (Pipelining) RESETMODE Selects Register Type CSDECODE Chip Select Decode WRITEMODE Read/Write Mode ENABLE GSR Enable or Disable Global Set Reset INITVAL Initialization Value 0x000000000000000000000000000000000000 The Single Port RAM (RAM_DQ) can be configured as NORMAL, READ BEFORE WRITE or WRITE THROUGH modes ...
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... Lattice Semiconductor Figure 9-10. Single Port RAM Timing Waveform - NORMAL Mode, with Output Registers Reset Clock t SUCE_EBR ClockEn WE t SUADDR_EBR Address Add_0 Data Data_0 t SUDATA_EBR Q Figure 9-11. Single Port RAM Timing Waveform - READ BEFORE WRITE Mode, without Output Registers Clock t SUCE_EBR ...
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... Lattice Semiconductor Figure 9-12. Single Port RAM Timing Waveform - READ BEFORE WRITE Mode, with Output Registers Reset Clock t SUCE_EBR ClockEn WE t SUADDR_EBR Address Data t SUDATA_EBR Q Figure 9-13. Single Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers Clock t SUCE_EBR ClockEn ...
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... Lattice Semiconductor Figure 9-14. Single Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers Reset Clock t SUCE_EBR ClockEn WE t SUADDR_EBR Address Add_0 Data Data_0 t SUDATA_EBR Q Invalid Data True Dual Port RAM (RAM_DP_TRUE) – EBR Based The EBR blocks in MachXO devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPexpress allows users to generate the Verilog-HDL, VHDL or EDIF netlists for various memory sizes depending on design requirements ...
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... Lattice Semiconductor Table 9-4. EBR based True Dual Port Memory Port Definitions Port Name in Generated Module ClockA, ClockB CLKA, CLKB ClockEnA, ClockEnB CEA, CEB AddressA, AddressB ADA[x1:0], ADB[x2:0] DataA, DataB DIA[y1:0], DIB[y2:0] QA, QB DOA[y1:0], DOB[y2:0] WrA, WrB WEA, WEB ResetA, ResetB ...
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... Lattice Semiconductor Table 9-6. MachXO Dual Port RAM Attributes Attribute Description DATA_WIDTH_A Data Word Width Port A DATA_WIDTH_B Data Word Width Port B Register Mode (Pipelining) REGMODE_A for Port A Register Mode (Pipelining) REGMODE_B for Port B RESETMODE Selects the Reset type Chip Select Decode ...
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... Lattice Semiconductor Figure 9-16. True Dual Port RAM Timing Waveform - NORMAL Mode, without Output Registers ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 DataA Data_A0 t SUDATA_EBR QA ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 DataB Data_B0 t SUDATA_EBR QB Memory Usage Guide for MachXO Devices ...
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... Lattice Semiconductor Figure 9-17. True Dual Port RAM Timing Waveform - NORMAL Mode with Output Register Reset ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 DataA Data_A0 t SUDATA_EBR QA ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 DataB Data_B0 t SUDATA_EBR QB Memory Usage Guide for MachXO Devices ...
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... Lattice Semiconductor Figure 9-18. True Dual Port RAM Timing Waveform - READ BEFORE WRITE Mode, without Output Regis- ters ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 New DataA Data_A0 t SUDATA_EBR QA Invalid Data ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 New DataB Data_B0 ...
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... Lattice Semiconductor Figure 9-19. True Dual Port RAM Timing Waveform - READ BEFORE WRITE Mode, with Output Registers Reset ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 New DataA Data_A0 t SUDATA_EBR QA Invalid Data ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 New DataB Data_B0 ...
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... Lattice Semiconductor Figure 9-20. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 DataA Data_A0 t SUDATA_EBR QA Invalid Data ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 DataB Data_B0 t SUDATA_EBR QB Invalid Data Memory Usage Guide for MachXO Devices ...
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... Lattice Semiconductor Figure 9-21. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers Reset ClockA t SUCE_EBR ClockEnA WrA t SUADDR_EBR AddressA Add_A0 DataA Data_A0 t SUDATA_EBR QA Invalid Data ClockB t SUCE_EBR ClockEnB WrB t SUADDR_EBR AddressB Add_B0 DataB Data_B0 t SUDATA_EBR QB Invalid Data ...
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... Lattice Semiconductor Pseudo Dual Port RAM (RAM_DP)- EBR Based The EBR blocks in the MachXO devices can be configured as Pseudo-Dual Port RAM or RAM_DP. IPexpress allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design require- ments. IPexpress generates the memory module as shown in Figure 9-22. ...
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... Lattice Semiconductor Diamond or ispLEVER software automatically generates the additional address decoding logic, which is imple- mented in the PFU external to the EBR blocks. Each EBR block consists of 9,216 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block for the devices are as per Table 9-8 ...
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... Lattice Semiconductor Figure 9-23. PSEUDO DUAL PORT RAM Timing Diagram – without Output Registers WrClock t SUCE_EBR WrClockEn RdClock RdClockEn t SUADDR_EBR WrAddress t SUADDR_EBR RdAddress Data t SUDATA_EBR Q Figure 9-24. PSEUDO DUAL PORT RAM Timing Diagram – with Output Registers WrClock t SUCE_EBR WrClockEn RdClock ...
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... Lattice Semiconductor Figure 9-25. ROM – Read Only Memory Module Generated by IPexpress OutClockEn The generated module makes use of these EBR blocks or primitives. For the memory sizes smaller than an EBR block, the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR blocks can be cascaded, in depth or width (as required to create these sizes) ...
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... Lattice Semiconductor Figure 9-26. ROM Timing Waveform – without Output Registers OutClock t SUCE_EBR OutClockEn Address t SUADDR_EBR Q Invalid Data Figure 9-27. ROM Timing Waveform – with Output Registers Reset OutClock t SUCE_EBR OutClockEn Address t SUADDR_EBR Q First In First Out (FIFO, FIFO_DC) - EBR Based The EBR blocks in MachXO devices can be configured as Dual Clock First In First Out Memories, FIFO_DC. IPex- press allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size, according to design requirements ...
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... Lattice Semiconductor A clock is always required, as only synchronous write is supported. The various ports and their definitions for the FIFO_DC are listed in Table 9-11. Table 9-11. EBR-based FIFO_DC Memory Port Definitions Port Name in Generated Module Port Name in Primitive CLKR CLKW WE RE RST DI DO ...
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... Lattice Semiconductor Table 9-13. FIFO and FIFO_DC Attributes for MachXO Attribute DATA_WIDTH_W Data Width Write Mode DATA_WIDTH_R Data Width Read Mode REGMODE Register Mode RESETMODE Select Reset Type CSDECODE_W Chip Select Decode for Write Mode CSDECODE_R Chip Select Decode for Read Mode ...
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... Lattice Semiconductor Similarly, data can be read from the FIFO_DC from the address pointed to by the read counter at the positive edge of the read clock when read enable is asserted. Read Pointer Reset (RPReset) is used to indicate a retransmit, and is more commonly used in “packetized” com- munications ...
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... Lattice Semiconductor Figure 9-29. FIFO_DC without Output Registers (Non-Pipelined) Reset RPReset WrClock t SUWREN_EBR WrEn RdClock RdEn Data Data_0 Data_1 t t SUDATA_EBR HDATA_EBR Q Full AlmostFull Empty AlmostEmpty Figure 9-30. FIFO_DC with Output Registers (Pipelined) Reset RPReset WrClock t SUWREN_EBR WrEn RdClock RdEn Data ...
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... Lattice Semiconductor Distributed Single Port RAM (Distributed_SPRAM) – PFU Based PFU based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create larger distributed memory sizes. Figure 9-31 shows the Distributed Single Port RAM module as generated by IPexpress. ...
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... Lattice Semiconductor Figure 9-32. PFU-Based Distributed Single Port RAM Timing Waveform – Without Output Registers Clock ClockEn t SUWREN_PFU WE t SUADDR_PFU Address Add_0 Data Data_0 t SUDATA_PFU Q Invalid Data Figure 9-33. PFU-Based Distributed Single Port RAM Timing Waveform - With Output Registers Reset Clock ...
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... Lattice Semiconductor Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create larger distributed memory sizes. Figure 9-34. Distributed Dual Port RAM Module Generated by IPexpress ...
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... Lattice Semiconductor Figure 9-35. PFU-Based Distributed Dual Port RAM Timing Waveform – without Output Registers (Non- Pipelined) WrClock t SUCE_EBR WrClockEn WE t SUADDR_EBR WrAddress Add_0 RdAddress Data Data_0 t SUDATA_EBR Q Memory Usage Guide for MachXO Devices t HCE_EBR t HADDR_EBR Add_1 Add_2 Add_0 Data_1 Data_2 ...
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... Lattice Semiconductor Figure 9-36. PFU-Based Distributed Dual Port RAM Timing Waveform – with Output Registers (Pipelined) Reset WrClock t SUWREN_PFU WrClockEn RdClock RdClockEn t SUWREN_PFU WE t SUADDR_PFU WrAddress Add_0 RdAddress Data Data_0 t SUDATA_PFU Q Memory Usage Guide for MachXO Devices t HWREN_PFU t SUCE_PFU t HWREN_PFU t HADDR_PFU ...
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... Lattice Semiconductor Distributed ROM (Distributed_ROM) – PFU Based PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create larger distributed memory sizes. Figure 9-37 shows the Distributed ROM module as generated by IPexpress. Figure 9-37. Distributed ROM Generated by IPexpress OutClockEn The generated module makes use of the 4-input LUT available in the PFU ...
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... Lattice Semiconductor Figure 9-39. PFU-Based ROM Timing Waveform – with Output Registers Reset OutClock OutClockEn t SUADDR_PFU Address Q Initializing Memory In the EBR based ROM or RAM memory modes and the PFU based ROM memory mode possible to specify the power-on state of each bit in the memory array. Each bit in the memory array can have one of two values ...
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... Lattice Semiconductor 00000110000001100000011000000110 00000111000001110000011100000111 00001000010010000000100001001000 00001001010010010000100101001001 00001010010010100000101001001010 00001011010010110000101101001011 00001100000011000000110000001100 00001101001011010000110100101101 00001110001111100000111000111110 00001111001111110000111100111111 00010000000100000001000000010000 00010001000100010001000100010001 00010010000100100001001000010010 00010011000100110001001100010011 Hex File The hex file is essentially a text file of hex characters arranged in a similar row-column arrangement. The number of rows in the file is same as the number of address locations, with each row indicating the content of the memory location ...
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... Lattice Semiconductor Revision History Date — April 2006 October 2006 September 2007 October 2010 Memory Usage Guide for MachXO Devices Version — Previous Lattice releases. 01.2 Updated the Initializing Memory section. 01.3 Added dual port memory access notes in Appendix A. 01.4 Updated FIFO_DC without Output Registers (Non-pipelined) and FIFO_DC with Output Registers (Pipelined) waveforms ...
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... Lattice Semiconductor Appendix A. Attribute Definitions DATA_WIDTH Data width is associated with the RAM and FIFO elements. The DATA_WIDTH attribute defines the number of bits in each word. It takes the values defined in the RAM size tables in each memory module. REGMODE REGMODE, or the Register mode attribute, is used to enable pipelining in the memory. This attribute is associated with the RAM and FIFO elements ...
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... Figure 10-2 shows the block diagram of the PLL. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Figure 10-2. PLL Block Diagram RST CLKI CLKI Divider CLKFB CLKFB Divider DDAMODE DDAIZR DDAILAG DDAIDEL[2:0] Features • Clock synthesis • Phase shift/duty cycle selection • Internal, clock tree and external feedback • Dynamic delay adjustment • No external components required • ...
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... Lattice Semiconductor CLKOK Divider The CLKOK divider feeds the global clock net. It divides the CLKOP signal of the PLL by the value of the divider. It can be set to values 6,....126,128. PLL Inputs and Outputs CLKI Input The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the Sheet in order for the PLL to operate correctly ...
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... Lattice Semiconductor nally registered by this clock recommended to assert PLL RST to re-synchronize the PLL to the reference clock. The LOCK signal is available to the FPGA routing to implement generation of RST. ModelSim models take two to four reference clock cycles from RST release to LOCK high. PLL Attributes The PLL utilizes several attributes that allow the configuration of the PLL through source constraints ...
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... Lattice Semiconductor Figure 10-4. MACHXO PLL Primitive Symbols Table 10-2. MachXO PLL I/O Definitions Signal I/O CLKI I General routing or dedicated global clock input pad. From general routing, clock tree, internal feedback from CLKOP or dedicated external feedback CLKFB I pad. RST I “1” to reset PLL counters. ...
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... Lattice Semiconductor Table 10-3. MachXO PLL User Attributes (Continued) MM GUI Attributes Access Duty Cycle Selection Y (1/8 Increment) Delay Control Y Feedback Mode Y CLKOS Select Y CLKOK Select Y 1. DYNAMIC This mode switches delay control between Dynamic and Static depending upon the input logic of DDAMODE pin. ...
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... Lattice Semiconductor Figure 10-5. Pre-Map Preference Editor Dynamic Delay Adjustment The Dynamic Delay Adjustment is controlled by the DDAMODE input. When the DDAMODE input is set to “1”, the delay control is done through the inputs, DDAIZR, DDAILAG and DDAIDEL(2:0). For this mode, the attribute “ ...
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... Lattice Semiconductor Table 10-4. Delay Adjustment DDAMODE = 1: Dynamic Delay Adjustment DDAIZR DDAILAG Don’t Care MachXO PLL Usage in IPexpress The MachXO PLL is fully supported by IPexpress in ispLEVER and Diamond design software. Figure 10-6 shows the main window when PLL is selected. To see screen shots of IPexpress in the Diamond soft- ware environment, see Appendix A, Figure 10-17 ...
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... Lattice Semiconductor Figure 10-6. IPexpress Main Window Configuration Tab The Configuration Tab lists all user accessible attributes with default values set. Upon completion of entries, click on Generate to generate source and constraint files. The user may choose to use the .lpc file to load parameters. ...
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... Lattice Semiconductor Frequency Mode In this mode, the user enters input and output clock frequencies and the software calculates the divider settings for user. If the output frequency the user entered is not achievable, the nearest frequency will be displayed in the Actual text box. After input and output frequencies are entered, clicking the Calculate button will display the divider values ...
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... Lattice Semiconductor Divider Mode In this mode, the user sets the divider settings with input frequency. The user must choose the CLKOP Divider value to maximize the f to achieve optimum PLL performance. After input frequency and divider settings are VCO complete, clicking the Calculate button will display the frequencies. Figure 10-8 shows the Divider Mode Configura- tion tab ...
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... Lattice Semiconductor Equations for generating Divider Settings and Output Frequency Ranges for Divider Mode Users The divider names are abbreviated with legacy names as follows: CLKI DIVIDER: M CLKFB DIVIDER: N CLKOP DIVIDER: V CLKOK DIVIDER Constraint VCO From the loop (N/ (1) OUT IN From the loop: ...
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... Lattice Semiconductor out of range PFD Assume M =1 Then 40*3/1 = 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .within range OUT f = 120 * 4 = 480 . . . . . . . . . . . within range but not an optimum value VCO 120 / .within range PFD In this case will satisfy all conditions 120*6 = 720 < 840 VCO Oscillator (OSCC) There is a dedicated oscillator in the MachXO device whose output is made available for user. ...
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... Lattice Semiconductor PCLK PIO (Primary Clock Pads) There are two PCLK PIOs on top and two PIOs on bottom, for a total of four pins for each MachXO device. These pads connect directly to the global clock network. PLL PIO There are two pad pairs (one pad pair on the upper side and one pair on the lower side) for the MachXO2280 and one pad pair for the MachXO1200 ...
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... Lattice Semiconductor Secondary Clock/CE/LSR Mux Connectivity The Secondary Clock/CE/LSR Mux input sources include: • Primary Clock input pins • From routing The Secondary Clock/CE/LSR Mux outputs feed four clock input switch boxes and eight control input switch boxes in each PFU. Each slice includes one clock input switch box and two control input switch boxes, one for CE (Clock Enable) and the other for LSR (Local Set/Reset) ...
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... Lattice Semiconductor Figure 10-14. Primary Clock and Secondary Clock/CE/LSR Distribution Primary Clock Net 4 Global Clocks 6 From Routing CLKOP CLKOS PLL CLKOK 6 Outputs CLKOP CLKOS CLKOK Secondary Clock/CE/LSR Net 12 From Routing 4 Global Clocks Maximum Number of Secondary Clocks Available As illustrated in Figure Figure 10-14, there are four secondary clock nets in the clock distribution network but only three of them are reaching the clock input mux at PFU ...
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... Lattice Semiconductor Figure 10-15. Post-Map Preference Editor Example PCB Layout Recommendations for V Available It is best to connect VCC to V PLL under it (tied via a single point to GND). Separate islands for both VCC PLL Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi ...
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... Lattice Semiconductor Revision History Date July 2005 October 2005 September 2006 February 2010 October 2010 Version 01.0 Initial release. 01.1 OSC frequency range changed. Total number of secondary clocks available is 3. ispLEVER GUI screen shot updated for version 5.1. References to MM/IP Manager replaced with IPexpress CLKOS/CLKOK select attributes added ...
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... Lattice Semiconductor Appendix A. Lattice Diamond Design Software Screen Shots Figure 10-16. Pre-Map Preference Editor in Diamond Figure 10-17. IPexpress Main Window in Diamond MachXO sysCLOCK PLL Design and Usage Guide 10-19 ...
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... Lattice Semiconductor Figure 10-18. MachXO PLL Configuration Tab (Frequency Mode) in Diamond Figure 10-19. MachXO PLL Configuration Tab (Divider Mode) in Diamond MachXO sysCLOCK PLL Design and Usage Guide 10-20 ...
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... Lattice Semiconductor Figure 10-20. Post-Map Preference Editor Example in Diamond MachXO sysCLOCK PLL Design and Usage Guide 10-21 ...
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... The power equations used in the Power Calculator are shown below. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Total DC Power (Resource) = Total DC Power of Used Portion + Total DC Power of Unused Portion = [DC Leakage per Resource when Used * N + [DC Leakage per Resource when Unused * (N Where the total number of resources in a device TOTAL RESOURCE N is the number of resources used in the design RESOURCE The total DC power consumption for all the resources as per the design data is the Quiescent Power in the Power Calculator ...
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... Lattice Semiconductor Starting the Power Calculator The user may launch the Power Calculator using one of two methods. The first method is by clicking the Power Calculator button in the toolbar as shown in Figure 11-1. Figure 11-1. Starting Power Calculator From the Toolbar Alternatively, users can launch the Power Calculator by going to the Tools menu and selecting Power Calculator as shown in Figure 11-2 ...
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... Lattice Semiconductor Figure 11-2. Starting Power Calculator from Tools Menu The Power Calculator does not support some of Lattice’s older devices. The toolbar button and menu item is only present when supported devices are selected. Creating a Power Calculator Project After starting the Power Calculator, the user will see the Power Calculator window. Click on File -> Menu and select New to get to the Start Project window, as shown in Figure 11-3 ...
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... Lattice Semiconductor Figure 11-3. Power Calculator Start Project Window (Create New Project) The Start Project window is used to create a new Power Calculator project (*.pep project). Three pieces of data must be input into the Start Project window: 1. The Power Calculator project name by default is the same as the Project Navigator project name. This can be changed, if desired ...
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... Lattice Semiconductor Figure 11-4. Power Calculator Main Window (Type View) The top pane of the window shows information about the device family, device and the part number as it appears in the Project Navigator. The V used for the power calculation is also listed. Users have a choice of selecting the ...
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... Lattice Semiconductor Some of the cells are shaded yellow in the tool. These cells are editable cells and users can type in values such as frequency, activity factors and resource utilization. The second tab, the Report tab, is the summary of the Power View. This report is in text format and provides the details of the power consumption. ...
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... Lattice Semiconductor Figure 11-6. Power Calculator Start Project Window (Using the New Project Window Wizard) The next screen allows users to select the device family, device and appropriate part number for which users plan to estimate power. After making the proper selections, click “Continue” (see Figure 11-7). ...
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... Lattice Semiconductor In the following screens, as shown in Figures 8-12, users can select further resources, like I/O types, clock name, frequency at which the clock is running, and other parameters, by selecting the appropriate resource using the pull- down menu: 1. Routing Resources 2. Logic 3. EBR 4. I/O 5. PLL 6 ...
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... Lattice Semiconductor Figure 11-9. Power Calculator Wizard Mode - Main Window Power Calculator - Creating a New Project Without the NCD File When starting a new project without the NCD file, begin either by using the Wizard (as discussed above selecting the Create a New Project option in the Power Calculator -> Start Project. Users are required to provide a project name and project directory ...
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... Lattice Semiconductor Figure 11-10. Power Calculator Main Window - Adding Resources This adds a new row for the logic resource utilization with clock domain as clk_1. Similarly, users can add other resources like EBR, I/Os, PLLs, routing, etc. Each of these resources is for the AC power estimation and categorized by clock domains. ...
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... Lattice Semiconductor Figure 11-11. Power Calculator Start Project Window with Post PAR NCD File The information from the NCD file is automatically inserted into the correct rows. Power Calculator uses the clock names from the design as shown in Figure 11-12. Power Estimation and Management ...
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... Lattice Semiconductor Figure 11-12. Power Calculator Main Window - Resource Utilization Picked up from the NCD File Power Calculator - Open Existing Project The Power Calculator - Start Project window also allows users to open an existing project. Select the option Open Existing Project, browse to the *.pep project file and click Continue. This opens the existing project in similar win- dows, as discussed above ...
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... Lattice Semiconductor Figure 11-13. Opening an Existing Project in the Power Calculator Power Calculator - Importing Simulation File (VCD) to the Project Users can import the post simulation VCD file into the power calculator project to estimate their design’s activity factors. Select Open Simulation File option under the File menu, browse to the VCD file location and select Open ...
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... Lattice Semiconductor Figure 11-14. Importing Simulation File in the Existing Project in the Power Calculator Power Calculator - Importing Trace Report File (TWR) to the Project Users can import the post Trace TWR file into the Power Calculator project to estimate their design’s activity fac- tors ...
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... Lattice Semiconductor Figure 11-15. Importing Trace Report File in the Existing Project in the Power Calculator Activity Factor and Toggle Rate Activity Factor% (or AF%) is defined as the percentage of frequency (or time) that a signal is active or toggling of the output. Most of the resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running ...
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... Lattice Semiconductor The most common examples are tance Junction-to-Case (also in °C/W). Another factor is Knowing the reference (i.e. ambient, case or board) temperature, the power and the relevant value, the junction temp can be calculated as per the following equations. + ( ...