HEF4059BP NXP Semiconductors, HEF4059BP Datasheet - Page 3

IC, DIVIDE-BY-N COUNTER, PROG, DIP-24

HEF4059BP

Manufacturer Part Number
HEF4059BP
Description
IC, DIVIDE-BY-N COUNTER, PROG, DIP-24
Manufacturer
NXP Semiconductors
Datasheet

Specifications of HEF4059BP

Counter Type
Divide-By-N, Programmable
Clock Frequency
20MHz
Count Maximum
16
Supply Voltage Range
4.5V To 15.5V
Logic Case Style
DIP
No. Of Pins
24
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HEF4059BP
Manufacturer:
PHILIPS
Quantity:
18
Part Number:
HEF4059BP
Manufacturer:
PHI
Quantity:
2
Philips Semiconductors
The three mode selection inputs K
the modulus (‘divide-by’ number) of the first and last
counting sections in accordance with Table 1.
Every time the first (fastest) counting section goes through
one cycle, it reduces, by 1, the number that has been
preset (jammed) into the three decades of the intermediate
counting section and into the last counting section (which
consists of flip-flops that are not needed for operating the
first counting section).
For example, in the
in the first counting section. Therefore the last (5th)
counting section has three flip-flops that can be preset to a
maximum count of seven with a place value of thousands.
This counting mode is selected when K
to HIGH. In this case input J
counting section and J
(5th) counting section.
If 10 mode is desired for the first section, K
K
used to preset the first counting section and there is no last
counting section. The intermediate counting section
consists of three cascaded BCD decade ( 10) counters,
presettable by means of the jam inputs J
When clock pulses are applied to the clock input after a
The mode select inputs permit frequency-synthesizer
channel separations of 10, 12,5, 20, 25 and 50 parts.
These inputs set the maximum value of n at 9999 (when
the first counting section divides by 5 or 10) or at 15 999
(when the first counting section divides by 8, 4 or 2).
The three decades of the intermediate counting section
can be preset to a binary 15 instead of a binary 9. In this
case the first cycle of a counter consists of 15 count
pulses, the next cycles consisting of 10 count pulses. Thus
the place value of the three decades are still 1, 10 and 100.
For example, in the
intermediate counting section begins to count-down can
be preset to:
January 1995
3rd
2nd decade:
1st
b
Programmable divide-by-n counter
J
to HIGH and K
L
1
decade:
decade:
J
4
L
2
J
H
c
1500
1665
3
to LOW. The jam inputs J
150
15
2 mode, only one flip-flop is needed
8 mode, the number from which the
2
to J
J
H
1
4
4
1
are used to preset the last
is used to preset the first
J
H
5
a
, K
b
a
, K
and K
J
L
5
6
b
to J
and K
a
5
1
is set HIGH,
c
16
to J
determine
J
H
.
7
c
4
are set
are
J
L
8
3
number n has been preset into the counter, the counter
counts down until the DETECTION circuit detects the zero
state. At this time the PRESET ENABLE circuit is enabled
to preset again the number n into the counter and to
produce an output pulse.
The preset of the counter to a desired
follows:
n = (MODE*) (1000
* MODE = first counting section divider (10, 8, 5, 4 or 2).
To calculate preset values for any n count, divide the
n count by the selected mode. The resultant is the
corresponding preset values of the 5th to the 2nd decade
with the remainder being equal to the 1st decade value.
If n = 8479, and the selected mode = 5, the preset value
= 8479
inputs must be set as follows:
The last counting section can be preset to a maximum of
1, with a place value of 1000. The total of these numbers
(2665) times 8 equals 21 320. The first counting section
can be preset to a maximum of 7. Therefore, 21 327 is the
maximum possible count in the
count of the various modes is shown in Table 1, in the
column entitled ‘extended counter range’. Control inputs
K
the ‘master preset’ mode. In this condition the flip-flops in
the counter are preset in accordance with the jam inputs
and the counter remains in that mode as long as K
K
the preset state when a counting mode other than the
‘master preset’ mode is selected. Whenever the ‘master
preset’ mode is used, control signals K
must be applied for at least 3 full clock pulses. After the
master preset mode inputs have been changed to one of
the counting modes, the next positive-going clock
transition changes an internal flip-flop so that the
count-down can begin at the second positive-going clock
transition. Thus, after a ‘master preset’ mode, there is
always one extra count before the output goes HIGH.
J
H
b
c
9
both remain LOW. The counter begins to run down from
and K
preset value
100
1
J
L
10
c
5 = 1695 with a remainder of 4, thus the jam
can be used to initiate and lock the counter in
decade 2 preset)
9
decade 4 preset
J
L
11
=
--------------- -
mode
n
decade 5 preset
˙
J
H
12
.
J
decade 1 preset.
L
13
10
8 mode. The highest
Product specification
decade 3 preset
J
H
HEF4059B
14
b
n is achieved as
= L and K
6
J
H
15
LSI
c
b
= L
and
J
L
16

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