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MC74VHC1GT08DFT1
MC74VHC1GT08DFT1 | |
|---|---|
| Manufacturer Part Number | MC74VHC1GT08DFT1 |
| Description | IC, SINGLE AND GATE, 2I/P, SOT-353-5 |
| Manufacturer | ON Semiconductor |
| MC74VHC1GT08DFT1 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
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Specifications of MC74VHC1GT08DFT1 | |||
|---|---|---|---|
| Output Current | 8mA | No. Of Inputs | 2 |
| Supply Voltage Range | 3V To 5.5V | Logic Case Style | SOT-353 |
| No. Of Pins | 5 | Operating Temperature Range | -55°C To +125°C |
| Logic Type | AND Gate | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
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MC74VHC1GT08
2−Input AND Gate/CMOS
Logic Level Shifter
The MC74VHC1GT08 is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT08 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT08 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
V
= 0 V. These input and output structures help prevent device
CC
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
•
High Speed: t
= 3.5 ns (Typ) at V
PD
•
= 1 mA (Max) at T
Low Power Dissipation: I
CC
•
TTL−Compatible Inputs: V
= 0.8 V; V
IL
•
CMOS−Compatible Outputs: V
> 0.8 V
OH
•
Power Down Protection Provided on Inputs and Outputs
•
Balanced Propagation Delays
•
Pin and Function Compatible with Other Standard Logic Families
•
Chip Complexity: FETs = 64; Equivalent Gates = 15
•
Pb−Free Packages are Available
IN B
1
IN A
2
3
GND
Figure 1. Pinout
IN A
&
IN B
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 10
= 5 V
CC
= 25°C
A
= 2 V
IH
; V
< 0.1 V
@Load
CC
OL
CC
5
V
CC
4
OUT Y
(Top View)
OUT Y
1
http://onsemi.com
MARKING
DIAGRAMS
5
5
1
SC−88A/SOT−353/SC−70
VT M G
DF SUFFIX
CASE 419A
1
5
5
VT M G
1
TSOP−5/SOT−23/SC−59
1
DT SUFFIX
CASE 483
VT
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
IN B
2
IN A
3
GND
4
OUT Y
5
V
CC
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHC1GT08/D
G
G
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|
MC74VHC1GT08DFT1 Summary of contents |
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