HEF4094BP NXP Semiconductors, HEF4094BP Datasheet
HEF4094BP
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HEF4094BP Summary of contents
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... Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information − ° All types operate from +125 Type number Package Name HEF4094BP DIP16 HEF4094BT SO16 HEF4094BTS SSOP16 power supply range referenced ° C. Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package ...
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... NXP Semiconductors 4. Functional diagram D 2 8-STAGE SHIFT CP REGISTER 3 STR 8-BIT STORAGE 1 REGISTER OE 15 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 Fig 1. Functional diagram STAGE LATCH 0 STR OE Fig 3. Logic diagram HEF4094B_8 Product data sheet QS2 10 QS1 001aaf119 Fig 2. STAGES ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin STR QP0 to QP7 14, 13, 12 QS1 9 QS2 HEF4094B_8 Product data sheet HEF4094B STR QP4 QP0 4 13 QP5 5 12 QP1 QP6 QP2 6 11 QP7 7 10 QP3 ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Inputs CP OE STR ↑ ↓ ↑ ↑ ↑ ↓ [1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs HIGH voltage level LOW voltage level don’t care; ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions |I | < 1 μA V HIGH-level IH O input voltage |I | < 1 μA V LOW-level IL O input voltage |I | < 1 μA V HIGH-level OH O output voltage |I | < 1 μA V LOW-level OL O output voltage I HIGH-level output current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter t HIGH to LOW PHL propagation delay t LOW to HIGH PLH propagation delay, t transition time t t OFF-state to HIGH PZH propagation delay t OFF-state to LOW PZL propagation delay t HIGH to OFF-state PHZ ...
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... NXP Semiconductors Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter t LOW to OFF-state PLZ propagation delay t set-up time su t hold time h t pulse width W f maximum frequency max [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C Table 8 ...
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... NXP Semiconductors 11. Waveforms QPn, QS1 output QS2 output Measurement points are given in Logic levels: V and Fig 6. Clock to outputs propagation delays, and clock pulse width and maximum frequency Table 9. Measurement points Supply voltage Input 0.5V DD STR input QPn output Measurement points are given in ...
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... NXP Semiconductors OE input LOW-to-OFF OFF-to-LOW HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 8. 3-state output enable and disable times for OE input QPn, QS1, QS2 output Measurement points are given in Logic levels: V and Fig 9. Data input data set up and hold times ...
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... NXP Semiconductors a. Input waveform b. Test circuit Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance load resistance termination resistance should be equal to the output impedance Z T Fig 10. Test circuit Table 10. Test data ...
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... NXP Semiconductors 12. Application information Some examples of applications for the HEF4094B are: • Serial-to-parallel data conversion • Remote control holding register DIGITALLY CONTROLLED (REQUIRES CONTINUOUS DIGITAL CONTROL) QP0 D CONTROL AND SYNC CIRCUITRY data clock from remote control panel Fig 11. Remote control holding register ...
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... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 14. Package outline SOT338-1 (SSOP16) ...
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... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4094B_8 20100402 • Modifications: Section 4 “Functional diagram” HEF4094B_7 20091216 • Modifications: Section 11 “Waveforms” Figure 10 “Test • Section 11 “Waveforms” Table 10 “Test data” values updated. HEF4094B_6 20091103 HEF4094B_5 20090728 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: HEF4094B_8 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 08 — 2 April 2010 HEF4094B 8-stage shift-and-store register © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Application information Package outline ...