IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet

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IS43/46DR81280A, IS43/46DR16640A 1Gb (x8, x16) DDR2 SDRAM FEATURES • Clock frequency up to 400MHz • 8 internal banks for concurrent operation • 4-bit prefetch architecture • Programmable CAS Latency and 7 • Programmable Additive Latency: 0, ...

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IS43/46DR81280A, IS43/46DR16640A Package Ball-out and Description DDR2 SDRAM (128Mx8) TW-BGA Ball-out (Top-View) (8.00mm x 13.65mm Body, 0.8mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command control pins A[13:0] Address BA[2:0] Bank Address DQ[7:0] ...

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IS43/46DR81280A, IS43/46DR16640A DDR2 SDRAM (64Mx16) TW-BGA Ball-out (Top-View) (8.00mm x 13.65mm Body, 0.8mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command control inputs A[12:0] Address BA[2:0] Bank Address DQ[15:0] I/O UDQS, UDQS# Upper ...

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IS43/46DR81280A, IS43/46DR16640A Functional Description Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for ...

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IS43/46DR81280A, IS43/46DR16640A Initialization Sequence after Power-Up Diagram tCH tCL ~ ~ CK tIS CK ODT ~ ~ PRE Command ~ NOP EMRS ALL 400ns tRP DLL Enable Programming the Mode Register and Extended Mode Registers For application ...

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IS43/46DR81280A, IS43/46DR16640A Mode Register (MR) Diagram Address Mode Field Register BA2 0 BA1 0 BA0 0 (1) 0 A13 A12 PD1 A11 A10 DLL CAS A5 Latency Burst A1 Length ...

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IS43/46DR81280A, IS43/46DR16640A DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh ...

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IS43/46DR81280A, IS43/46DR16640A Extended Mode Register 2 (EMR[2]) Diagram Address Mode Field Register BA2 0 BA1 1 BA0 0 (1) 0 A13 (1) 0 A12 (1) 0 A11 (1) 0 A10 ( ( SRFt (1) 0 ...

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IS43/46DR81280A, IS43/46DR16640A Truth Tables Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal ...

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IS43/46DR81280A, IS43/46DR16640A Clock Enable (CKE) Truth Table (2) Current State (1) Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H Notes: 1. CKE (N) is the logic state of ...

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IS43/46DR81280A, IS43/46DR16640A Commands DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. ...

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IS43/46DR81280A, IS43/46DR16640A required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, ...

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IS43/46DR81280A, IS43/46DR16640A ODT Timing for Active/Standby (Idle) Mode and Standard Active Power-Down Mode CK CKE ~ tIS ODT ~ Internal Term. ~ Resistance Notes: 1. Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and ...

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IS43/46DR81280A, IS43/46DR16640A Absolute Maximum DC Ratings Symbol VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss Vin, Vout Voltage on any pin relative to Vss ...

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IS43/46DR81280A, IS43/46DR16640A AC and DC Logic Input Levels Single-ended DC Input Logic Level Symbol Parameter VIH(DC) DC input logic HIGH VIL(DC) DC input logic LOW Single-ended AC Input logic level Symbol Parameter VIH(AC) AC input logic HIGH VIL(AC) AC input ...

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IS43/46DR81280A, IS43/46DR16640A Differential Signal Level Waveform Differential AC Output Parameters Symbol Parameter VOX(AC) AC differential crosspoint voltage Note: The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to ...

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IS43/46DR81280A, IS43/46DR16640A Output Buffer Characteristics Output AC Test Conditions Symbol VOTR Output Timing Measurement Reference Level Note: The VDDQ of the device under test is referenced. Output DC Current Drive Symbol IOH(DC) Output Minimum Source DC Current IOL(DC) Output Minimum ...

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IS43/46DR81280A, IS43/46DR16640A ODT DC Electrical Characteristics Parameter/Condition Rtt effective impedance value for EMRS(A6=0, A2=1); 75 ohm Rtt effective impedance value for EMRS(A6=1, A2=0); 150 ohm Rtt effective impedance value for EMRS(A6=A2=1); 50 ohm Deviation of VM with respect to VDDQ/2 ...

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IS43/46DR81280A, IS43/46DR16640A IDD Specifications and Conditions IDD Measurement Conditions Symbol Parameter/Condition Operating Current - One bank Active - Precharge: IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus ...

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IS43/46DR81280A, IS43/46DR16640A IDD Specifications Symbol Configuration x8 IDD0 x16 x8 IDD1 x16 IDD2P x8/x16 IDD2N x8/x16 x8 IDD2Q x16 IDD3Pf x8/x16 IDD3Ps x8/x16 IDD3N x8/x16 x8 IDD4R x16 x8 IDD4W x16 IDD5B x8/x16 IDD5D x8/x16 IDD6 x8/x16 x8 IDD7 x16 ...

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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Row Cycle Time tRC Auto Refresh Row tRFC Cycle Time Row Active Time tRAS Row Active to Column Address tRCD Delay tRRD(x8) Row Active to Row Active Delay ...

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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Input Setup Time (fast tIS slew rate) Input Hold Time (fast slew tIH rate) Input Pulse Width tIPW Write DQS High Level tDQSH Width Write DQS Low Level ...

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IS43/46DR81280A, IS43/46DR16640A AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol DQ to Low Impedance from tLZ(DQ) CK/CK# Mode Register Set Delay tMRD OCD Drive Mode Output tMOD Delay ODT Drive Mode Output Delay Exit Self refresh to Non-Read ...

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IS43/46DR81280A, IS43/46DR16640A 3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW. 4. The output timing reference voltage level is VTT. 5. The values tCL(min) ...

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IS43/46DR81280A, IS43/46DR16640A Reference Loads, Slew Rates and Slew Rate Derating 1. Reference Load for Timing Measurements Figure AC Timing Reference Load represents the timing reference load used in defining the relevant timing parameters of the part not intended ...

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... CL-t -t Order Part No 5-5-5 IS43DR81280A-3DBL IS43DR16640A-3DBL 6-6-6 IS43DR81280A-25EBL IS43DR16640A-25EBL 5-5-5 IS43DR16640A-25DBL = -40°C to +85°C A CL-t -t Order Part No 5-5-5 IS43DR81280A-3DBLI IS43DR16640A-3DBLI IS43DR16640A-3DBI 6-6-6 IS43DR81280A-25EBLI IS43DR16640A-25EBLI 5-5-5 IS43DR81280A-25DBLI IS43DR16640A-25DBLI = -40°C to +85°C A CL-t -t Order Part No 5-5-5 IS46DR81280A-3DBLA1 IS46DR16640A-3DBLA1 6-6-6 IS46DR81280A-25EBLA1 IS46DR16640A-25EBLA1 5-5-5 IS46DR81280A-25DBLA1 IS46DR16640A-25DBLA1 = -40° ...

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IS43/46DR81280A, IS43/46DR16640A PACKAGE OUTLINE DRAWING 60-ball TW-BGA: Fine Pitch Ball Grid Array Outline (x8) Integrated Silicon Solution, Inc. – www.issi.com – Rev. B, 06/01/2011 27 ...

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IS43/46DR81280A, IS43/46DR16640A 84-ball TW-BGA: Fine Pitch Ball Grid Array Outline (x16) Integrated Silicon Solution, Inc. – www.issi.com – Rev. B, 06/01/2011 28 ...