IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet - Page 12

no-image

IS43DR16640A-3DBL

Manufacturer Part Number
IS43DR16640A-3DBL
Description
SDRAM, DDR2, 64M X 16, 1.8V, 84BGA
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS43DR16640A-3DBL

Access Time
0.45ns
Memory Case Style
BGA
No. Of Pins
84
Memory Type
SDRAM
Memory Configuration
8 BLK (8M X 16)
Page Size
1GB
Operating Temperature Range
0°C To +70°C
Frequency
333MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS43DR16640A-3DBL
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16640A-3DBL
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS43DR16640A-3DBL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS43DR16640A-3DBLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16640A-3DBLI
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS43DR16640A-3DBLI
Manufacturer:
ISSI
Quantity:
8 206
IS43/46DR81280A, IS43/46DR16640A
required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a
REFRESH command.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When
in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF) must be
maintained at valid levels upon entry/exit and during SELF REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon
entering self refresh and is automatically enabled upon exiting self refresh.
ODT (On-Die Termination)
The On-Die Termination feature allows the DDR2 SDRAM to easily implement an internal termination resistance (Rtt). For the x8
option, ODT can be configured for DQ[7:0], DQS, DQS#, DM, RDQS, and RDQS# signals. For the x16 option, ODT can be configured for
DQ[15:0], UDQS, LDQS, UDQS#, LDQS#, and UDM, and LDM signals. The ODT feature can be configured with the Extended Mode
Register Set (EMRS) command, and turned on or off using the ODT input signal. Before and after the EMRS is issued, the ODT input
must be received with respect to the timings of tAOFD, tMOD(max), tAOND; and the CKE input must be held HIGH throughout the
duration of tMOD(max).
The DDR2 SDRAM supports the ODT on and off functionality in Active, Standby, and Power Down modes, but not in Self Refresh
mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode.
EMRS to ODT Update Delay
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 06/01/2011
Command
ODT
CK#
CK
tAOFD
~
~
~
Old Setting
EMRS
tMOD(Min)
NOP
tMOD(Max)
NOP
NOP
ODT Ready
tIS
NOP
tAOND
~
~
~
NOP
Updated
12

Related parts for IS43DR16640A-3DBL